SNLA364C March   2021  – June 2022 DP83TD510E

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 1-V and 2.4-V p2p Mode Scripts
  5. 3 Time-Domain Reflectometry
    1. 3.1 TDR Application Startup
      1. 3.1.1 TDR_CFG (Address = 0x001E) [Reset = 0x0000]
      2. 3.1.2 TDR_Fault_Status (Address = 0x030C) [Reset = 0x0000]
    2. 3.2 TDR Test Procedure
  6. 4 Active Link Cable Diagnostics
    1. 4.1 ALCD Application Startup
    2. 4.2 ALCD Test Procedure
      1. 4.2.1 Cable Calibration
      2. 4.2.2 Cable Quality Measurement
  7. 5 Signal Quality Indicator
    1. 5.1 SQI Application Startup
      1. 5.1.1 MSE Detection (Address = 0x0A85 ) [Reset = 0x0000]
    2. 5.2 SQI Test Procedure
  8. 6 Cable Diagnostics Summary
  9. 7 Loopback Modes
    1. 7.1 BISCR (Address = 0x0016) [Reset = 0x0100]
  10. 8 Pseudo-Random Bit Sequence Functions
    1. 8.1 PRBS_CFG_1 (Address = 0x0119) [Reset = 0x0574]
    2. 8.2 PRBS_STATUS_4 (Address = 0x011F) [Reset = 0x0000]
  11. 9 USB to MDIO Procedure
  12. 10IEEE 802.3cg PMA Compliance
  13. 11Revision History

10 IEEE 802.3cg PMA Compliance

The DP83TD510E is IEEE 802.3cg 10Base-T1L compliant. The device supports all the required test modes within the standard for assessing PHY compliance.

When testing the PMA compliance of the DP83TD510E, it is necessary to configure the PHY into the appropriate test mode. The IEEE 802.3cg specifies three test modes to measure the transmitter’s waveform, distortion, jitter, and droop. The IEEE 802.3cg standard specifies limits for both 1.0 Vpp and 2.4 Vpp output operating modes.

Table 10-1 IEEE 802.3cg 10Base-T1L PMA Specifications
Test Limit
1.0 Vpp mode 2.4 Vpp mode
Output Voltage Maximum 1.05 mV 2.520 mV
Minimum 0.850 mV 2.040 mV
Droop Positive 10% 10%
Negative 10% 10%
Jitter 10 ns
PSD Mask Template Template
Power Level -0.2 – 2.2 dBm 7.4 – 9.8 dBm

The default output operating mode will be 1.0 Vpp without a link partner detected. Select the output operating mode of the DP83TD510E by running the script below for 2.4 Vpp in the 1-V and 2.4-V p2p mode session for the test mode 1, 2, and 3. 

//Set Output operating mode for 2.4 Vpp for test mode 1,2,and 3
begin
000D 0001
000E 08F6
000D 4001
000E 1000 //force 2.4V

000D 001F
000E 0016
000D 401F
000E 0104 //enable digital loopback to force link up to have three level signal
end
  1. Test Mode 1: Transmitter output voltage and timing jitter test mode.
    1. When the DP83TD510E is configured in test mode 1, the PHY repeats the data sequence (+1, -1). 
      begin
000d 0001 
000e 08f8
000d 4001
000e 2000 //Set test mode 1 in MMD 01
001f 4000 //soft reset
end
  2. Test Mode 2: Transmitter output droop test mode.
    1. When the DP83TD510E is enabled in test mode 2, the PHY repeats ten “+1” symbols followed by ten “-1” symbols. 
      begin
000d 0001 
000e 08f8
000d 4001
000e 4000 //Set test mode 2 in MMD 01
001f 4000 //soft reset
end
  3. Test Mode 3: Normal operation in Idle mode, to be used in PSD Mask tests.
    1. Test mode 3 sets the DP83TD510E in the MDI master mode transmitting normal Inter-Frame idle signals. 
      begin
000d 0001 
000e 08f8
000d 4001
000e 6000 //Set test mode 1 in MMD 01
001f 4000 //soft reset
end
  4. MDI Return Loss for slave mode: Slave Idle mode.
    1. 1V p2p MDI Return Loss compliance test.
      begin 

//001f 8000 //hard reset

000d 0007 
000e 0200 
000d 4007 
000e 0000 //disable autoneg MMD 07

000d 0001 
000e 0834 
000d 4001 
000e 0000 //Force Slave Mode MMD 01

000d 0001 
000e 08f6 
000d 4001 
000e 0000 //Force 1V swing MMD 01

001f 4000 //soft reset

end
    2. 2.4-V p2p MDI Return Loss compliance test.
      begin 

//001f 8000 //hard reset

000d 0007 
000e 0200 
000d 4007 
000e 0000 //disable autoneg MMD 07

000d 0001 
000e 0834 
000d 4001 
000e 0000 //Force Slave Mode MMD 01

000d 0001 
000e 08f6 
000d 4001 
000e 1000 //Force 2.4V swing MMD 01

001f 4000 //soft reset

end