SNLA416A September   2022  – February 2024 DS90UB960-Q1 , HD3SS3212-Q1

 

  1.   1
  2.   Abstract
  3. 1Market Need
  4. 2Multiplexing FPD-Link Scheme
  5. 3Multiplexing Execution and Setup
  6. 4Implementation of Switching Protocol
  7. 5Assessing Impact on Signal Integrity
    1. 5.1 Return Loss
    2. 5.2 Insertion Loss
  8. 6Margin Analysis
  9. 7Conclusion
  10. 8References

Multiplexing FPD-Link Scheme

For high-speed, high-resolution multiplexing applications, considering the impact on channel scattering parameters and link margin between the SER and DES is important to determine how the transmission channel is affected. This characterization was done using the setup shown in Figure 2-1.

The multiplexer intercepts the FPD-Link SerDes transmission channel on the deserializer side of the power over coax (PoC) connection. This allows for the DC component of the PoC connection to be removed prior to being fed into the multiplexer. The component then connects directly to the FPD-Link III RX Port 3 pins (RIN3+ and RIN3–). Switch the multiplexer according to the protocol described in Section 4, Implementation of Switching Protocol for proper function.

GUID-20220901-SS0I-4JHC-Q6JN-2BQ2KSBW046L-low.svg Figure 2-1 Multiplexing Testing Scheme