SNLA421 December   2022 DS320PR810 , SN75LVPE5412 , SN75LVPE5421

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Add-in-Card (AIC) Form Factor
  4. 2Compliance Tests
    1. 2.1 Workshop Test Results
    2. 2.2 Electrical Testing Results
  5. 3Electrical Performance
    1. 3.1 Effects of EQ Index on Time Domain Signal
    2. 3.2 Effects of EQ Index on the Eye Diagram
    3. 3.3 Effects of DC Gain on Time Domain Signal
    4. 3.4 Effects of DC Gain on the Eye Diagram
  6. 4Compliance Setting Fine Tuning
  7. 5Summary
  8. 6References

2.1 Workshop Test Results

Table 2-1 summarizes the PCI-SIG workshop interoperability results using the DS320PR810 AIC.

Table 2-1 Workshop Testing Summary
Test Number Test Group Vendor Test Description Test Results
1 Gen-5 Teledyne AIC TX/PLL Gold Endpoint Tester Pass
2 System Microchip Interoperability with Gen-5 root complex (x16) Pass
3 Gen-5 Keysight AIC link equalization Pass
4 System Alibaba Interoperability with Gen-5 root complex (x16) Pass
5 Gen-3 Teledyne AIC link equalization Pass
6 System Cadence Interoperability with Gen-5 root complex (x8) Pass
7 Gen-4 Tektronix AIC link equalization Pass
8 Gen-5 Keysight AIC TX PLL Pass
9 System Broadcom Interoperability with Gen-5 root complex (x16) Pass
10 Gen-5 Viavi Gen-5 lane margining, link transaction Pass
11 System Xilinx Interoperability with Gen-5 root complex (x8) Pass
12 Gen-5 PCI-SIG Golden Config. Configuration tests Pass