SNLU300 EVM User's guide

SNLU300A January 2023 – February 2023 DS160PR1601 , DS320PR1601

2.4 DS320PR1601 Channel Mapping

The DS320PR1601 divides the 32 channels of the device into 4 groups of 8 channels each. There are two Downstream groups and two Upstream groups. On the DS320PR1601RSC-EVM, the Downstream channels refer to channels where the data flows from CPU to DS320PR1601 to Endpoint. The Upstream channels refer to channels where the data flows from the Endpoint to DS320PR1601 to CPU. Table 2-4 lists the Downstream channel mapping of the DS320PR1601. Table 2-5 lists the Upstream channel mapping of the DS320PR1601.

Table 2-4 DS320PR1601 Downstream Channel Mapping

PCIe Lane	DS320PR1601 Channel	I2C ADDR CONFIG PINS		Channel Bank	Example I2C Address	Bank Channel#
0	A_PEx0	A_ADDR1_7-0 {Example Pin State = L0}	A_ADDR0_7-0 {Example Pin State = L0}	0	18h	0
1	A_PEx1				18h	1
2	A_PEx2				18h	2
3	A_PEx3				18h	3
4	A_PEx4			1	19h	4
5	A_PEx5				19h	5
6	A_PEx6				19h	6
7	A_PEx7				19h	7
8	A_PEx8	A_ADDR1_15-8 {Example Pin State = L0}	A_ADDR0_15-8 {Example Pin State = L1}	0	1Ah	0
9	A_PEx9				1Ah	1
10	A_PEx10				1Ah	2
11	A_PEx11				1Ah	3
12	A_PEx12			1	1Bh	4
13	A_PEx13				1Bh	5
14	A_PEx14				1Bh	6
15	A_PEx15				1Bh	7

Table 2-5 DS320PR1601 Upstream Channel Mapping

PCIe Lane	DS320PR1601 Channel	I2C ADDR CONFIG PINS		Channel Bank	Example I2C Address	Bank Channel#	PD pin control
0	B_PEx0	B_ADDR1_7-0 {Example Pin State = L0}	B_ADDR0_7-0 {Example Pin State = L2}	1	1Dh	7	PD_7_4
1	B_PEx1				1Dh	6	PD_7_4
2	B_PEx2				1Dh	5	PD_7_4
3	B_PEx3				1Dh	4	PD_7_4
4	B_PEx4			0	1Ch	3	PD_3_0
5	B_PEx5				1Ch	2	PD_3_0
6	B_PEx6				1Ch	1	PD_3_0
7	B_PEx7				1Ch	0	PD_3_0
8	B_PEx8	B_ADDR1_15-8 {Example Pin State = L0}	B_ADDR0_15-8 {Example Pin State = L3}	1	1Fh	7	PD_15_12
9	B_PEx9				1Fh	6	PD_15_12
10	B_PEx10				1Fh	5	PD_15_12
11	B_PEx11				1Fh	4	PD_15_12
12	B_PEx12			0	1Eh	3	PD_11_8
13	B_PEx13				1Eh	2	PD_11_8
14	B_PEx14				1Eh	1	PD_11_8
15	B_PEx15				1Eh	0	PD_11_8

Each channel of the DS320PR1601 features a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. Each channel has 20 equalization gain settings available through CTLE index selection. The equalization gain is set by writing registers in I2C mode. For more details, refer to the DS320PR1601 data sheet.