SNVU785B february   2022  – august 2023 TPS389006-Q1

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Related Documentation
    2. 1.2 TPS389006-Q1 Applications
  4. 2Schematic, Bill of Materials, and Layout
    1. 2.1 TPS389006Q1EVM Schematic
    2. 2.2 TPS389006Q1EVM Bill of Materials
    3. 2.3 Layout and Component Placement
    4. 2.4 Layout
  5. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  6. 4EVM Setup and Operation
    1. 4.1 Setup and GUI Installations
      1. 4.1.1 TPS389006Q1EVM Hardware Setup
      2. 4.1.2 TPS389006Q1EVM Software Setup
    2. 4.2 Quick Start to TPS389006Q1EVM GUI
    3. 4.3 Example Operation of TPS389xxx-Q1
  7. 5Revision History

3.1 EVM Test Points

Table 3-1 lists the EVM test points as well as their functional descriptions. All TPS389006-Q1 pins have a corresponding test point on the EVM. These test points are located close to the pins for more accurate measurements. In addition to the test points listed below, the EVM also has four additional GND test points.

Table 3-1 Test Points
TEST POINT SILKSCREEN LABEL FUNCTION DESCRIPTION
MON1 Connection to MON1 pin Allows the user to monitor voltage rail #1
MON2 Connection to MON2 pin Allows the user to monitor voltage rail #2
MON3 Connection to MON3 pin Allows the user to monitor voltage rail #3
MON4 Connection to MON4 pin Allows the user to monitor voltage rail #4
MON5/RS_4 Connection to MON5 pin Allows the user to monitor voltage rail #5
MON6/RS_3 Connection to MON6 pin Allows the user to monitor voltage rail #6
MON7/RS_1/2 Connection to RS_1/2 pin Allows the user to remote sense MON1 or MON2
SYNC/NRST/MON8 Connection to SYNC pin SYNC pin indicates the number of monitored rails that have exited fault status and assigns tag values to each monitor voltage rail
SYNC_PD Connection to SYNC_PD Forcing the SYNC pin to toggle during test and increments an internal tag counter for each of the monitored channel (for debug purposes only)
ADDR Connection to ADDR pin Allows the user to measure the I2C address voltage
NIRQ Connection to NIRQ pin Allows the user to monitor the interrupt (NIRQ) output
EN/ACT Connection to ACT pin Allows the user to set the ACT input to VDD or GND
SLEEP/ESM/WDI Connection to SLEEP pin Allows the user to set SLEEP input
SCL Connection to SCL pin Allows the user to monitor the clock signal input
SDA Connection to SDA pin Allows the user to monitor the data signal input
PEXT External power supply Allows the user to apply a power supply voltage that is not provided from the EVM
GND GND for EVM GND for EVM