SNVU864 October   2023 TPS3762-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Jumpers
      2. 2.1.2 EVM Test Points
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Input Supply Voltage (VDD)
      2. 2.2.2 SENSE
      3. 2.2.3 RESET
      4. 2.2.4 Built-In Self-Test (BIST)
      5. 2.2.5 Built-In Self-Test Enable and Latch Clear (BIST_EN / LATCH_CLR)
      6. 2.2.6 RESET Time Delay (CTR)
      7. 2.2.7 Sense Time Delay (CTS)
  7. 3Implementation Results
    1. 3.1 EVM Performance Results
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks

2.2.5 Built-In Self-Test Enable and Latch Clear (BIST_EN / LATCH_CLR)

The BIST_EN / LATCH_CLR is connected through TP4 on the board. Jumper J11 can also configure the BIST_EN / LATCH_CLR pin to also connect to TP11 (Refer to Table 3-1 for configuration options). The TPS3762-Q1 family of devices contain a Built-In Self-Test Enable and Latch Clear (BIST_EN / LATCH_CLR) pin for enabling the BIST, as well as clearing a BIST fault. The BIST_EN asserts BIST for a time period, TD_BIST. If BIST encounters a fault, then BIST remains asserted for a period longer than TD_BIST. LATCH_CLR requires a rising edge to clear the flagged fault on the BIST pin. Please refer to the device data sheet for additional details.