SPRAD67A
december 2022 – july 2023
AM6411
,
AM6412
,
AM6421
,
AM6422
,
AM6441
,
AM6442
1
Abstract
Trademarks
1
Introduction
1.1
Before Getting Started With the Board Design
1.2
Processor (Device) Selection
1.2.1
Availability of Tightly Coupled Memory (TCM)
1.3
Technical Documentation
1.4
Design Documentation
2
Block Diagram
2.1
Creating the Block Diagram
2.2
Selecting the Boot Mode
2.3
Confirming Pinmux (Multiplexing Compatibility)
3
Power Supply
3.1
Power Supply Architecture
3.1.1
Integrated Power Architecture
3.1.2
Discrete Power Architecture
3.2
Power (Supply) Rails
3.2.1
Core Supply
3.2.2
Peripheral Power Supply
3.2.3
Internal LDO for IO Groups (Processor IO Groups)
3.2.4
Dual-Voltage IOs (LVCMOS IOs / Processor IOs)
3.2.5
Dual-Voltage Dynamic Switching IOs for SDIO
3.2.6
VPP (eFuse ROM Programming Supply)
3.3
Determining Board Power Requirements
3.4
Power Supply Filters
3.5
Power Supply Decoupling and Bulk Capacitors
3.5.1
Note on PDN Target Impedance
3.6
Power Supply Sequencing
3.7
Supply Diagnostics
3.8
Power Supply Monitoring
4
Clocking
4.1
System Clock Input
4.2
Unused Clock Input
4.3
Clock Output
4.4
Single-ended Clock Source
4.5
Crystal Selection
5
JTAG (Joint Test Action Group)
5.1
JTAG / Emulation
5.1.1
Configuration of JTAG / Emulation
5.1.1.1
AM64x
5.1.1.2
AM243x
5.1.2
Implementation of JTAG / Emulation
5.1.3
JTAG Termination
6
Configuration (Processor) and Initialization (Processor and Device)
6.1
Processor Reset
6.2
Latching of the Boot Mode Configuration
6.3
Attach Device Reset
6.4
Watchdog Timer
7
Peripherals
7.1
Selecting Peripherals Across Domains
7.2
Memory
7.2.1
Processor DDR Subsystem and Device Register Configuration
7.3
Media and Data Storage Interfaces
7.4
Ethernet Interface
7.4.1
Common Platform Ethernet Switch 3-port Gigabit Ethernet (CPSW3G)
7.4.2
Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
7.5
Universal Serial Bus (USB) Subsystem
7.6
Peripheral Component Interconnect Express (PCIe) Subsystem
7.7
General Connectivity Peripherals
7.8
Analog-to-Digital Converter (ADC)
7.8.1
Change Summary of AM64x / AM243x SR2.0 ADC Errata
7.9
Termination of Power Pins, Unused Peripherals and IOs
7.9.1
External Interrupt (EXTINTn)
8
Interfacing of IO Buffers and Simulations
8.1
AM64x
8.2
AM243x
9
Power Consumption and Thermal Analysis
9.1
Power Consumption
9.2
Maximum Current for Different Supply Rails
9.3
Power Modes
9.4
Guidance on Thermal Design
9.4.1
AM64x
9.4.2
AM243x
10
Schematic Capture and Review
10.1
Selection of Components and Components Value
10.2
Schematic Capture
10.3
Reviewing the Schematics
11
Floor Planning, Layout and Routing Guidelines
11.1
Escape Routing Guidelines
11.2
DDR Layout Guidelines
11.3
High-Speed Differential Signal Routing Guidance
11.4
Additional References for Simulation
12
Device Handling and Assembly
13
References
13.1
AM64x
13.2
AM243x
13.3
Common
14
Terminology
15
Revision History
13.3
Common
Texas Instruments:
AM64x / AM243x Sitara Processors Technical Reference Manual
Texas Instruments:
AM64x / AM243x Processor Silicon Errata
Texas Instruments:
AM64x / AM243x Power Estimation Tool
Texas Instruments:
AM64x / AM243x Schematic Design and Review Checklist
Texas Instruments:
AM64x and AM243x BGA Escape Routing
Texas Instruments:
AM64x / AM243x DDR Board Design and Layout Guidelines
Texas Instruments:
AM62A3 / AM62A7 DDR Board Design and Layout Guidelines
Texas Instruments:
Thermal Design Guide for DSP and Arm Application Processors Application Report
Texas Instruments:
PRU-ICSS Feature Comparison
Texas Instruments:
Industrial Communication Protocols Supported on Sitara™ Processors and MCUs
Texas Instruments:
Sitara Processor Power Distribution Networks: Implementation and Analysis
Texas Instruments:
Emulation and Trace Headers Technical Reference Manual
Texas Instruments:
High-Speed Interface Layout Guidelines
Texas Instruments:
Hardware Design Guide for KeyStone II Devices