SPRADD4 October   2023 AM625SIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Via Channel Arrays
  6. 3 Width/Spacing Proposal for Escapes
  7. 4 Stackup
  8. 5 Via Sharing
  9. 6 Floorplan Component Placement
  10. 7 Critical Interfaces Impact Placement
  11. 8 Routing Priority
  12. 9 SerDes Interfaces
  13. 10Power Decoupling
  14. 11Route Lowest Priority Interfaces Last
  15. 12Summary

3 Width/Spacing Proposal for Escapes

The AM62xSiP Via channel array solution has been designed to support the following. The AM62xSiP package supports similar feature set as several other competition solutions with approximately 15% smaller package area and ~10% wider line width. This solution therefore, reduces PCB foot print and utilizes lower cost PCB rules enabling compact and low-cost systems.

Table 3-1 Width/Spacing Proposal for Escapes
PCB Feature PCB Routing Requirements Comments
Minimum via diameter 18 mils Via pads dia - 18 Mils
Via hole size 8 mils Via hole dia - 8 Mils
Minimum trace width/spacing required in the BGA breakout (Inner Layer) Trace Width - 3.2 Mils
Spacing - 3.2 Mils
Minimum trace width/spacing required in the BGA breakout (External Layer) Trace Width - 3.2 Mils
Spacing - 3.2 Mils
Number of layers used for escape 4 Layers Top
Ground
Power
Bottom
BGA land pad size 12 Mils
Package Size 13 mm x 13 mm
PCB layers (signal routing, total) recommended (2, 4) Layers Top
Ground
Power
Bottom