SPRUIW7A October 2020 – February 2022
INA226 power monitor devices are used to monitor current and voltage of various power rails of J7200 processor. The device reports current, voltage and power to J7200 processor through I2C interface. Four Terminal High Precision shunt resistors are provided, and the values are calculated based on load current.
POWER SOURCE | SUPPLY NET | I2C Bus | SLAVE ADDRESS (IN HEX) | Value of the Shunt Connected to the Supply Rail |
---|---|---|---|---|
VDD_MCU_0V85_REG | VDD_MCU_0V85 | SOC_I2C2/PM1 | 0x40 | 0.01E |
VDD_MCU_0V85_REG | VDD_MCU_RAM_0V85 | SOC_I2C2/PM1 | 0x41 | 0.01E |
VDA_MCU_1V8_REG | VDA_MCU_1V8 | SOC_I2C2/PM1 | 0x42 | 0.01E |
VDD_MCUIO_3V3_LS | VDD_MCUIO_3V3 | SOC_I2C2/PM1 | 0x43 | 0.01E |
VDD_MCUIO_1V8_REG | VDD_MCUIO_1V8 | SOC_I2C2/PM1 | 0x44 | 0.01E |
VDD_CORE_0V8_REG | VDD_CORE_0V8 | SOC_I2C2/PM1 | 0x45 | 0.005E |
VDD_RAM_0V85_REG | VDD_RAM_0V85 | SOC_I2C2/PM1 | 0x46 | 0.01E |
VDD_WK_0V8_REG | VDD_WK_0V8 | SOC_I2C2/PM1 | 0x47 | 0.01E |
VDD_CPU_AVS_REG | VDD_CPU_AVS | SOC_I2C2/PM1 | 0x48 | 0.01E |
VDD_DDR_1V1_REG | VDDR_BIAS_1V1 | SOC_I2C2/PM1 | 0x49 | 0.01E |
VDDR_IO_DV_SRC | VDDR_IO_DV | SOC_I2C2/PM1 | 0x4A | 0.01E |
VDD_CORE_0V8 | VDD_PHYCORE_0V8 | SOC_I2C2/PM1 | 0x4B | 0.01E |
VDA_PLL_1V8_REG | VDA_PLL_1V8 | SOC_I2C2/PM1 | 0x4C | 0.01E |
VDD_PHY_1V8_REG | VDD_PHY_1V8 | SOC_I2C2/PM1 | 0x4D | 0.01E |
VDD_USB_3V3_REG | VDA_USB_3V3 | SOC_I2C2/PM1 | 0x4E | 0.01E |
VDD_GPIORET_3V3 | VDD_GPIORET_3V3 | SOC_I2C2/PM1 | 0x4F | 0.01E |
VDD_IO_1V8_REG | VDD_IO_1V8 | SOC_I2C2/PM2 | 0x40 | 0.01E |
VDD_IO_3V3_LS | VDD_IO_3V3 | SOC_I2C2/PM2 | 0x41 | 0.01E |
VDD_SD_DV_REG | VDD_SD_DV | SOC_I2C2/PM2 | 0x42 | 0.01E |
VDD1_LPDDR4_1V8_REG | VDD1_LPDDR4_1V8 | SOC_I2C2/PM2 | 0x43 | 0.01E |
VDD_DDR_1V1_REG | VDD2_LPDDR4_1V1 | SOC_I2C2/PM2 | 0x44 | 0.01E |
VDDR_IO_DV_SRC | VDDQ_LPDDR4_DV | SOC_I2C2/PM2 | 0x45 | 0.01E |
VDD_MCUIO_1V8_REG | VSYS_MCUIO_1V8 | SOC_I2C2/PM2 | 0x46 | 0.01E |
VDD_MCUIO_3V3_LS | VSYS_MCUIO_3V3 | SOC_I2C2/PM2 | 0x47 | 0.01E |
VDD_IO_1V8_REG | VSYS_IO_1V8 | SOC_I2C2/PM2 | 0x48 | 0.01E |
VDD_IO_3V3_LS | VSYS_IO_3V3 | SOC_I2C2/PM2 | 0x49 | 0.01E |
VCC_12V0 | VCC_12V0 | SOC_I2C2/PM2 | 0x4A | 0.01E |
VSYS_5V0 | VSYS_5V0 | SOC_I2C2/PM2 | 0x4B | 0.01E |
VSYS_3V3 | VSYS_3V3 | SOC_I2C2/PM2 | 0x4C | 0.005E |
VSYS_3V3 | VSYS_3V3_SOM | SOC_I2C2/PM2 | 0x4D | 0.01E |
VDA_DLL_0V8_REG | VDA_DLL_0V8 | SOC_I2C2/PM2 | 0x4E | 0.01E |
EXP_3V3 | EXP_3V3 | SOC_I2C2/PM2 | 0x4F | 0.01E |
INA devices can be accessed from the processor through Main I2C2 instance. Also, there is an option to Monitor the SoC and peripheral powers using external I2C Master.
Common processor has five-pin header (J12) with isolation circuit to interface the INA devices with external I2C Master. Buffer IC SN74CB3Q3125PWR (U69) is used to isolate the External I2C connections from the INA devices. The control of this buffer is provided from SYS_PWR_PG, which is enabled by default on power up.
External Power Monitor header details:
Mfr. Part# 68002-205HL (CON HDR 1X5 2.54MM PITCH ST TH)
Header (J12) Pin Number | Signal Name |
---|---|
1 | CON_PM1_SCL |
2 | CON_PM1_SDA |
3 | DGND |
4 | CON_PM2_SDA |
5 | CON_PM2_SCL |
Test automation header on the Common processor board also can access these INA devices externally.