SPRUJ59 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
This section outlines the analog differences between F28003x and F28P55x. Three Programmable Gain Amplifiers(PGA) are a new addition to the F28P55x and there are now five ADCs vs the 3 ADCs on the F28003x device. There are several enhancements inside the CMPSS and ADC modules.
Module | Category | F28003x | F28P55x | Notes |
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Analog Sysctrl | HW Changes | - | Global Sychronous SW Trigger for ADC | Allows for SW Trigger to ADC sent to selected ADCs simultaneously |
- | New register for VREFHI selection | Support for per ADC VREFHI selection reference voltage:
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- | New register for VREFHI selection | Support for per ADC VREFLO selection reference voltage:
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- | Support for full 3.3V FSR with External VREFHI | Can supply 1.65V on VREFHI in external mode to have FSR = 3.3V | ||
- | 12mA Drive on Select GPIOs | For compatiblity with I2C and PMBUS High Speed + mode, GPIO 2/3/9/32 have option for 12mA drive strength | ||
- | 1.35V VIH compatibility on select GPIOs | Changes VIH for GPIO 2/3/9/32 to 1.35V | ||
Register | ANAREFCTL.ANAREFSEL | ANAREFPCTRL.REFPMUXSELx | x = ADC A/B/C/D/E Each ADC is now configured independently for VREFHI source | |
- | ANAREFNCTL.REFNMUXSELx | x = ADC A/B/C/D/E Each ADC has VREFLO selection capability | ||
ANAREFCTL.ANAREF2P5SEL | ANAREFPCTL.ANAREFx1P65SEL | x = ADC A/B/C/D/E Each ADC has independent 1.65V(3.3V FSR) or 2.5V FSR selection. Also effects external reference mode. | ||
- | IO_DRVSEL | Configure selected GPIO (IOL) drive strength for either 4mA(default) or 12mA (IOL) | ||
- | IO_MODESEL | Configure selected GPIO VIH to either 3.3V(default) or 1.35V | ||
ADC1 | Number | 3 - ADCA, ADCB, ADCC | 5 - ADCA, ADCB, ADCC, ADCD, ADCE | F28003x has Type 5 ADC F28P55x has Type 6 ADC |
Max Speed | 60 MHz | 75MHz | Max throughput is 3.9MSPS on the F28P55x vs 4MSPS on the F28003x device |
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HW Changes | - | New PPB
features
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- | ADC Repeater Logic | Ability to initiate subsequent triggers automatically, with option to add phase delay. Can use with PPB to realize oversampling without CPU overhead | ||
- | Global SW Force SOC Trigger | Ability to initiate a SW SOC trigger to all ADCs simultaneously | ||
- | ADC S/H Cap Reset | Ability to reset the S/H Cap to VSSA between samples | ||
Register | ADCTL1 | ADCTL1 | Addition of External Mux Control and DMA Trigger Timings | |
ADCSOCxCTL.TRIGSEL | ADCSOCxCTL.TRIGSEL | Increased Trigger Options for ePWM and repeat block support | ||
INTFLGCLR | ADCINTFLGCLR | |||
ADCINTSOCSEL2 | ADCINTSOCSEL1 | All SOC interrupt triggers moved to INTSOCSEL1 | ||
GPDAC | Number | 2 - GPDACA, GPDACB | 1- GPDACA | Type 1 GPDAC on both devices |
CMPSS1 | Number | 4 - CMPSS1 to CMPSS4 | 4 - CMPSS1 to CMPSS4 | F28003x has Type 2 CMPSS F28P55x has Type 6 CMPSS |
HW changes |
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Registers | RAMPMAXREFA | RAMPHREFA | Register Name Change | |
RAMMAXREFS | RAMPHREFS | Register Name Change | ||
RAMPDECVALA | RAMPHSTEPVALA | Register Name Change | ||
RAMPDECVALS | RAMPHSTEPVALS | Register Name Change | ||
RAMPSTS | RAMPHSTS | Register Name Change | ||
RAMPDLYA | RAMPHDLYA | Register Name Change | ||
RAMPDLYS | RAMPHDLYS | Register Name Change | ||
CTRIPLFILCTL | CTRIPLFILCTL - Field Changes | Additions and changes to fields within this register. For more details, see the device-specific TRMs. | ||
CTRIPLFILCLKCTL | CTRIPLFILCLKCTL - Field Changes | Increased prescalar range | ||
CTRIPHFILCTL | CTRIPHFILCTL - Field Changes | Additions and changes to fields within this register. For more details, see the device-specific TRMs. | ||
CTRIPHFILCLKCTL | CTRIPHFILCLKCTL - Field Changes | Increased prescalar range | ||
- | COMPDACLCTL | Register and functionality added to support dual ramp generators | ||
- | RAMPLREFA | Register and functionality added to support dual ramp generators | ||
- | RAMPLREFS | Register and functionality added to support dual ramp generators | ||
- | RAMPLSTEPVALA | Register and functionality added to support dual ramp generators | ||
- | RAMPLSTEPVALS | Register and functionality added to support dual ramp generators | ||
- | RAMPLSTS | Register and functionality added to support dual ramp generators | ||
- | RAMPLDLYA | Register and functionality added to support dual ramp generators | ||
- | RAMPLDLYS | Register and functionality added to support dual ramp generators | ||
- | CTRIPLFILCLKCTL2 | Register and functionality added to support dual ramp generators | ||
- | CTRIPHFILCLKCTL2 | Register and functionality added to support dual ramp generators | ||
Temp Sensor | Number | 1 - (in ADCC ch 12) | 1 - (in ADCC ch12) |