SPRUJ59 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F28003x and F28P55x
    1. 1.1 F28003x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ, 80-Pin PNA and 64-Pin PM Packages
    2. 2.2 100-Pin PZ, 80-Pin PNA and 64-Pin PM Migration Between F28003x and F28P55x For New and Existing PCB
    3. 2.3 GPIO Input Buffer Control Register
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1 Programmable Gain Amplifier(PGA)
      2. 3.1.2 Universal Serial Bus (USB)
      3. 3.1.3 5V Failsafe IOs
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
      4. 3.5.4 SW Libraries Included in the ROM
      5. 3.5.5 AGPIO
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F28003x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 PGA
    2. 5.2 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References

3.5.1 PLL

The PLL blocks of F28003x and F28P55x devices are the same, however the maximum PLL Raw Clock for F28P55x is higher to accommodate the SYSCLK frequency requirement of F28P55x. Table 3-4 lists the PLL features for both devices for comparison. for more information, consult the TMS320F28P55x microcontrollers technical reference manual.

Table 3-4 PLL Features
Feature F28003x F28P55x
Max CPU Clock 120 MHz 150 MHz
VCO Range 220 - 600 MHz 220 - 600 MHz
PLL Raw Clock Range 6 - 240 MHz 6- 300 MHz
X1 Input Range (PLL enable) 2 - 25 MHz 2 - 25 MHz
REFCLK Divider Yes [1..32] Yes [1..32]
PLL Slip Detect No (use DCC) No (use DCC)
Fractional PLLMULT No No