SPRY345B february   2022  – april 2023 DP83TG720R-Q1 , DP83TG720S-Q1 , TCAN1043A-Q1

 

  1.   At a glance
  2.   Authors
  3.   Introduction
  4.   Overcoming E/E architecture challenges
  5.   Power distribution challenges and solutions
  6.   Decentralization of power distribution
  7.   Replacing melting fuses with semiconductor fuses
  8.   Smart sensor and actuator challenges and solutions
  9.   Zonal modules –new microcontroller requirements
  10.   Smart sensors and actuators
  11.   Data challenges and solutions
  12.   Types of data
  13.   Time sensitivity of data
  14.   Communication security
  15.   Conclusion

Time sensitivity of data

To accommodate different latency or QoS requirements, Ethernet-based time-sensitive networks (TSN) are a good option, but this deployment needs a lot of fine-tuning; older MCUs and processors might not even support this fully in hardware. PHY IC-level or switch support can help, especially considering time synchronization.

In many cases, the integration of multiple Ethernet ports in a single SoC can be a big advantage to save on board space and cost.

For audio, many infotainment architectures already use audio video bridging (AVB), for which time synchronization is important (see the TI E2E™ technical article, “Optimizing eAVB for Automotive Applications Using Clock Generators”). AVB networks are well proven, but they are agnostic to many concurrency problems when deployed in a domain architecture. With the move to a zone architecture, which combines all kind of data traffic, the newer TSN features gain importance.

Table 1 lists some Institute of Electrical and Electronics Engineers (IEEE) TSN standards that could be relevant for zone architecture implementations. For more information, see the white paper, “Time-Sensitive Networking for Industrial Automation.”

Table 1 Some relevant TSN standards for automotive real-time applications.
Standard Alias Description
IEEE 802.1AS Timing and synchronization Provides Layer 2 time synchronization
IEEE 802.1Qbv Time aware shaper
(now: enhancements for scheduled traffic)		 Runs the 8-port output queues of a bridge on a rotating schedule. Blocks all ports except one based on a time schedule in order to prevent delays during scheduled transmission.
IEEE 802.3br Interspersed express traffic Interrupts transmission of an ordinary frame to transmit an “express” frame, then resumes the ordinary.
IEEE 802.1Qbu Frame pre-emption Improves the interruption of non-time-critical frames to enable time-critical frame throughput.
IEEE 802.1CB Redundancy Messages are copied and communicated in parallel over disjoint paths; redundant duplicates are removed at the receiver end.
IEEE 802.1Qch Cyclic queuing and forwarding Collects packets according to their traffic class and forwards them in one cycle. Provides a simple way to use TSN if controlled timing is a priority but reducing latency isn’t important (can be covered by IEEE 802.1AS and IEEE 802.1Qbv).
IEEE 802.1Qci Per-stream filtering and policing Filters frames on ingress ports based on arrival times, rates and bandwidth to protect against excess bandwidth usage and burst sizes, as well as against faulty or malicious endpoints.
IEEE 802.1Qav Traffic-based credit shaper Avoids bursts of frame (same class or stream); change priorities between traffic classes or streams.

For audio use cases, latency targets are less strict than for powertrain or chassis control use cases (milliseconds versus microseconds). But even when routing a lot of meta or configuration data traffic or a massive amount of ADAS sensor data through the same network, the audio latency requirement cannot be violated – packets cannot be dropped. That’s why arbitration and fine-tuning of the existing TSN knobs is important. One well-known knob is time aware shaping (TAS), available in TI’s processor SDK referenced as enhancements for scheduled traffic (EST) offload. TAS guarantees the transfer of lower-bandwidth traffic after a pre-defined time window, no matter how much other data (such as ADAS sensor data) is transported in parallel. In the best case, integrating the TSN hardware switch as in TI’s processors, such as DRA821, offers full software flexibility, while being supported by hardware accelerators for data packet handling and forwarding or willingly dropping.