SPRZ426E November   2014  – February 2021 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726

 

  1. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  2. 2Silicon Advisories
    1.     Revisions SR 2.1, 2.0, 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i782
    14.     i783
    15.     i802
    16.     i803
    17.     i807
    18.     i808
    19.     i809
    20.     i810
    21.     i813
    22.     i814
    23.     i815
    24.     i818
    25.     i819
    26.     i820
    27.     i824
    28.     i826
    29.     i829
    30.     i834
    31.     i849
    32.     i856
    33.     i862
    34.     i863
    35.     i867
    36.     i868
    37.     i869
    38.     i870
    39.     i871
    40.     i872
    41.     i874
    42.     i875
    43.     i878
    44.     i879
    45.     i880
    46.     i881
    47.     i882
    48.     i883
    49.     i887
    50.     i889
    51.     i890
    52.     i893
    53.     i895
    54.     i896
    55.     i897
    56.     i898
    57.     i899
    58.     i900
    59.     i903
    60.     i904
    61.     i906
    62.     i913
    63.     i916
    64.     i927
    65.     i928
    66.     i929
    67.     i930
    68.     i932
    69.     i933
    70.     i940
  3. 3Silicon Limitations
    1.     Revisions SR 2.1, 2.0, 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i876
    10.     i877
    11.     i892
    12.     i909
    13.     i917
  4. 4Silicon Cautions
    1.     Revisions SR 2.1, 2.0, 1.0 - Cautions List
    2.     i781
    3. 4.1 93
    4.     i827
    5.     i832
    6.     i836
    7.     i839
    8.     i864
    9.     i885
    10.     i886
    11.     i912
    12.     i918
    13.     i920
    14.     i926
    15.     i931
    16.     i934
    17. 4.2 107
  5. 5Revision History

Modules Impacted

Table 1-1 Silicon Advisories, Limitations, and Cautions by Module
MODULEDESCRIPTIONSILICON REVISIONS AFFECTED
DRA72xDRA71x
1.02.02.02.1
NAi781: Power Delivery Network VerificationYesYesYesYes
i862: Reset Should Use PORzYesYesYesYes
i864: VDDS18V to VDDSHVn Current PathYesYesYesYes
i931: VDD to VDDA_"PHY" Current PathYesYesYesYes
i934: VDDA_PCIE to VDDA33V_USB1 Current PathYesYes
ATLi933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
BOOTi875: Power-on-Reset (PORz) Warm Boot HangYes
i927: SoC Doesn’t Read Redundant ONFI Parameter Pages in NAND Boot ModeYesYesYes
CAMSSi709: CSI-2 Receiver Executes Software Reset UnconditionallyYesYesYesYes
i904: CSI Interface Setup/Hold Timing Does Not Meet MIPI DPHY Spec above 600MHzYesYesYesYes
i913: CSI2 LDO Needs to Be Disabled when Module Is Powered OnYes
Control Modulei813: Spurious Thermal Alert Generation When Temperature Remains in Expected RangeYesYesYesYes
i814: Bandgap Temperature Read Dtemp Can Be CorruptedYesYesYesYes
i827: Thermal Alert Will Not Be Generated When Bandgap Is Configured in "Smart Idle" ModeYesYesYesYes
i863: MMC2 Has PU/PD Contention Immediately after Release from ResetYesYesYesYes
i869: IO Glitches Can Occur When Changing IO SettingsYesYesYesYes
i870: PCIe Unaligned Read Access IssueYesYesYesYes
i885: Software Requirements for Data Manual IO TimingYesYesYesYes
i900: SoC Will Hang If Region 5 Accessed While CTRL_CORE_MMR_LOCK_5 Is LockedYesYesYesYes
DCANi893: DCAN Initialization SequenceYesYesYesYes
i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
DEBUGi879: DSP MStandby Requires CD_EMU in SW_WKUPYesYesYesYes
i928: JTAG: Boundary Scan (BSDL) Cannot Control Select Signals When resetn is HighYesYesYes
DMAi378: sDMA Channel Is Not Disabled after a Transaction ErrorYesYesYesYes
i698: DMA4 Generates Unexpected Transaction on WR PortYesYesYesYes
i699: DMA4 Channel Fails to Continue with Descriptor Load When Pause Bit Is ClearedYesYesYesYes
i868: McASP to EDMA Synchronization Level Event Can Be LostYes
DSPi872: DSP MFlag Output Not InitializedYesYesYesYes
i879: DSP MStandby Requires CD_EMU in SW_WKUPYesYesYesYes
i883: DSP Doesn't Wake from Subsystem Internal InterruptsYesYesYesYes
i898: DSP Pre-fetch Should Be Disabled before Entering Power Down ModeYesYesYesYes
DSSi596: BITMAP1-2-4 Formats Not Supported by The Graphics PipelineYesYesYesYes
i631: Wrong Access in 1D Burst for YUV4:2:0-NV12 FormatYesYesYesYes
i641: Overlay Optimization LimitationsYesYesYesYes
i734: LCD1 Gamma Correction is Not Working When GFX Pipe Is DisabledYesYesYesYes
i815: Power Management Enhancement Implemented Inside DSS Leads to DSS UnderflowsYesYesYesYes
i829: Reusing Pipe Connected to Writeback Pipeline On -the-Fly to an Active PanelYesYesYesYes
i838: DSS BT.656/BT.1120 Max Horizontal Blanking is Non CompliantYesYesYesYes
i920: Dual-rank DDR with Twin Die Configuration is Not SupportedYesYes
i932: DPLL_VIDEOn May Require Multiple Lock AttemptsYesYesYesYes
EDMAi844: EDMA to VCP Stream Burst is Not FunctionalYesYesYesYes
i868: McASP to EDMA Synchronization Level Event Can Be LostYes
EMIFi727: Refresh Rate Issue after Warm ResetYesYesYesYes
i729: DDR Access Hang after Warm ResetYesYesYesYes
i878: MPU Lockup with Concurrent DMM and EMIF AccessesYesYesYesYes
i882: EMIF: DDR ECC Corrupted Read/Write Status ResponseYes
i895: EMIF_FW: System Hang When EMIF Firewall Is Reconfigured While There Is Activity on EMIF InterfaceYesYesYesYes
i918: Dual-rank DDR with Twin Die Configuration is Not SupportedYesYesYesYes
eMMC/SD/SDIOi802: MMCHS DCRC Errors During Tuning ProcedureYesYesYesYes
i803: MMCHS Read Transfer with CMD23 Never Complete When BCE=0 And ADMA UsedYesYesYesYes
i832: DLL SW Reset Bit Does Not Reset to 0 after ExecutionYesYesYesYes
i834: MMCHS HS200 and SDR104 Command Timeout Window Too SmallYesYesYesYes
i836: Bus Testing Commands CMD19 Incorrectly Waits for CRC Status ReturnYesYesYesYes
i856: 32k Oscillator Fails to Start-Up at PORYesYesYesYes
i863: MMC2 Has PU/PD Contention Immediately after Release from ResetYesYesYesYes
i887: MMC3 Speed Limited to 64 MHzYesYesYesYes
i890: MMC1 IOs and PBIAS Must Be Powered-Up Before IsolationYesYesYesYes
i929: MMC1/2 SDR104/HS200 Mode DLL Delay Value May Result In Unexpected Tuning Pattern ErrorsYesYesYesYes
GMAC_SWi877: RGMII Clocks Should Be Enabled at Boot TimeYesYesYesYes
i880: Ethernet RGMII2 Limited to 10/100 MbpsYes
i899: Ethernet DLR Is Not SupportedYesYesYesYes
i903: Ethernet RMII Interface RMII_MHZ_50_CLK Not Supported as Output Reference ClockYesYesYesYes
GPIOi856: 32k Oscillator Fails to Start-Up at PORYesYesYesYes
GPMCi927: SoC Doesn’t Read Redundant ONFI Parameter Pages in NAND Boot ModeYesYesYes
I2Ci694: System I2C Hang Due to Miss of Bus Clear SupportYesYesYesYes
i833: I2C Module in Multislave Mode Potentially Acknowledges Wrong AddressYesYesYesYes
i930: I2C1 and I2C2 May Drive Low During ResetYesYesYesYes
INTCi883: DSP Doesn't Wake from Subsystem Internal InterruptsYesYesYesYes
Interconnecti871: L4_PER3 Firewall Initiator ConnID Value Left-Shift 1-BitYesYesYesYes
McASPi848: McASP IO Pad Loopback Not FunctionalYesYesYesYes
i868: McASP to EDMA Synchronization Level Event Can Be LostYes
i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
MLBi881: MLB: Potential for Misaligned Data in Multi-Frame per Sub-Buffer ModeYesYesYesYes
i917: MLB 3072Fs, 4096Fs Not SupportedYes
i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
MPUi878: MPU Lockup with Concurrent DMM and EMIF AccessesYesYesYesYes
i940: MPU COUNTER_REALTIME saturates after several hundred days Yes Yes Yes Yes
PCIei870: PCIe Unaligned Read Access IssueYesYesYesYes
i906: USB3.0 and PCIe Gen2 Electrical ComplianceYes
i909: PCIe Unintentional Translation of Outbound Message TLPsYesYesYesYes
i926: PCIe Preferred PCIe_PHY_RX SCP Register Settings UpdatedYesYesYesYes
PRCMi810: DPLL Controller Can Get Stuck While Transitioning to a Power Saving StateYesYesYesYes
i826: HSDIVIDER1 CLKOUT4 Could Glitch During On-the-Fly Divider Change to/from Divide-by-2.5YesYesYesYes
i876: DVFS Only Supported on MPUYesYesYesYes
i886: FPDLink PLL Unlocks with Certain SoC PLL M/N ValuesYesYesYesYes
i892: L3 Clocks Should Be Enabled at All TimesYesYesYesYes
PWMSSi933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
QSPIi912: QSPI_SPI_CMD_REG [25:24] Masked from Read in RTLYesYesYesYes
i916: QSPI Reads Can Fail For Flash Devices with HOLD FunctionYesYesYesYes
SATAi782: SATA AHCI Command Issue OrderYesYes
i783: SATA Lockup after SATA DPLL Unlock/RelockYesYes
i807: SATA Host Controller Locks up If PIO Setup FIS Is Received and Bus Busy and Data Request Bits Are ClearedYesYes
i808: SATA Link Locks up under Certain ConditionsYesYes
i809: SATA Command Does Not Complete and Software Must Issue a Port Reset Under Certain ConditionsYesYes
i818: SATA PHY Reset Required Following SATA PLL UnlockYesYes
TIMERSi767: Delay Needed to Read Some Timer Registers After WakeupYesYesYesYes
i856: 32k Oscillator Fails to Start-Up at PORYesYesYesYes
i874: TIMER5/6/7/8 Interrupts Not PropagatedYesYesYesYes
UART/IrDA/CIRi202: MDR1 Access Can Freeze UART ModuleYesYesYesYes
i849: UART2_RXD Is Not Working for MUXMODE=0YesYesYesYes
i889: UART Does Not Acknowledge Idle Request after DMA Has Been EnabledYesYesYesYes
i933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
USBi819: A Device Control Bit Meta-Stability for USB3.0 Controller in USB2.0 ModeYesYesYesYes
i820: Unexpected USB Link State Value upon U3 Exit by USB3.0 LinkYesYesYesYes
i824: USB3.0 Link Cannot Be Established When Suspend Mode Is EnabledYesYesYesYes
i845: USB2.0 False Detection of Disconnect ConditionYesYesYesYes
i867: USB SuperSpeed LFPS Signal Is Not Compliant with the USB3.0 StandardYes
i896: USB xHCI Port Disable Feature Does Not WorkYesYesYesYes
i897: USB xHCI Stop Endpoint Command Does Not Work in Certain CircumstancesYesYesYesYes
i906: USB3.0 and PCIe Gen2 Electrical ComplianceYes
VCPi933: Access to IODELAY at Same Time as Other Peripheral on L4_PER2 Can HangYesYesYesYes
VIPi839: Some RGB and YUV Formats Have Non-Standard OrderingYesYesYesYes
VPEi839: Some RGB and YUV Formats Have Non-Standard OrderingYesYesYesYes