DRA714 600 MHz ARM Cortex-A15 SoC processor with graphics & DSP for infotainment & cluster | TI.com

DRA714 (ACTIVE) 600 MHz ARM Cortex-A15 SoC processor with graphics & DSP for infotainment & cluster

 

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Description

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solutions.

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.

The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.

Features

  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) interconnects
  • DDR3/DDR3L Memory Interface (EMIF) module
    • Supports up to DDR-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller With DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • Single-core PowerVR™ SGX544 3D GPU
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
    • Up to two external ports
  • Sixteen 32-bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Six high-speed inter-integrated circuit (I2C) ports
  • HDQ™/1-Wire® interface
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI Interface (QSPI)
  • Media Local Bus Subsystem (MLBSS)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High-speed USB 2.0 dual-role device
  • High-speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane Gen2-compliant port
    • or two 1-lane Gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® CSI-2 camera serial interface
  • Up to 186 General-Purpose I/O (GPIO) pins
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

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Parametrics

Compare all products in DRAx infotainment SoCs Email Download to Excel
Part number Order Arm CPU Arm MHz (Max.) DSP DSP MHz (Max) Graphics acceleration DRAM Co-processor(s) Hardware accelerators EMIF Other on-chip memory CSI-2 EMAC Video input ports Display Serial I/O MMC/SD PCIe McASP Security enabler USB
DRA714 Order now 1 ARM Cortex-A15     600     1 C66x     400
750    
1 2D
1 3D    
DDR3-1066
DDR3L-1066    
2 Dual ARM Cortex-M4     1 Image Video Accelerator
2 Viterbi Decoder
1 Audio Tracking Logic    
1 32-bit     512 KB     2 DL     10/100/1000
2-port 1Gb switch    
4     1 HDMI OUT
2 LCD OUT    
CAN
I2C
SPI
UART
USB    
1x SDIO 4b
1x SDIO 8b
1x UHSI 4b
1x eMMC 8b    
2 PCIe Gen2     8     Cryptographic acceleration
Debug security
Device identity
Secure boot
Secure storage
Trusted execution environment    
1 USB3.0
2 USB2.0    
DRA710 Samples not available 1 ARM Cortex-A15     600         1 2D     DDR3-1066
DDR3L-1066    
  1 Image Video Accelerator
2 Viterbi Decoder
1 Audio Tracking Logic    
1 32-bit     512 KB     2 DL     10/100/1000
2-port 1Gb switch    
4     1 HDMI OUT
2 LCD OUT    
CAN
I2C
SPI
UART
USB    
1x SDIO 4b
1x SDIO 8b
1x UHSI 4b
1x eMMC 8b    
2 PCIe Gen2     8     Cryptographic acceleration
Debug security
Device identity
Secure boot
Secure storage
Trusted execution environment    
1 USB3.0
2 USB2.0    
DRA712 Samples not available 1 ARM Cortex-A15     600         1 2D
1 3D    
DDR3-1066
DDR3L-1066    
2 Dual ARM Cortex-M4     1 Image Video Accelerator
2 Viterbi Decoder
1 Audio Tracking Logic    
1 32-bit     512 KB     2 DL     10/100/1000
2-port 1Gb switch    
4     1 HDMI OUT
2 LCD OUT    
CAN
I2C
SPI
UART
USB    
1x SDIO 4b
1x SDIO 8b
1x UHSI 4b
1x eMMC 8b    
2 PCIe Gen2     8     Cryptographic acceleration
Debug security
Device identity
Secure boot
Secure storage
Trusted execution environment    
1 USB3.0
2 USB2.0    
DRA716 Samples not available 1 ARM Cortex-A15     800     1 C66x     400
750    
1 2D
1 3D    
DDR3-1333
DDR3L-1333    
2 Dual ARM Cortex-M4     1 Image Video Accelerator
2 Viterbi Decoder
1 Audio Tracking Logic