SPRZ519 august 2023 IWR2243
High-Speed Data System Coupling to the Clock System
IWR2243 ES1.0, ES1.1
Data transfer over LVDS and CSI interface with repeatable patterns could interfere with the clock system and cause low-level spurs in the Rx spectrum and show up in the 2D-FFT. In case of CSI interface, the mode transitions (LP-to-HS or HS-to-LP) could also cause interference in the clock system.
The firmware allows applying random dither to the CSI data transfer start time. This can be controlled using the "IWR_DEV_CSI2_DELAY_DUMMY_CFG_SET_SB" API. With the dithering the glitch on the synthesizer frequency error gets spread out in time, across the chirps of a frame, reducing the impact in the 2D-FFT.