TIDUDA6A December   2017  – January 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

3.1 Analog Input Front End

The TIDA-01022 platform has flexible analog inputs to validate system performance with two different input paths:

  • Transformer coupling:

    The transformer coupling consists of an onboard Marki balun, which supports a 500-kHz to 6-GHz input bandwidth with 6-dB insertion loss. The transformer coupling functions to validate the ADC12DJ3200 device performance at the AC input signal.

  • Fully differential amplifier (LMH5401 + LMH6401):

    The LMH5401+LMH6401 path that drives the ADC12DJ3200 can either be DC coupled or AC coupled at the inputs. A typical DC-coupled configuration uses an LMH6401 device to produce a balanced differential output signal for the ADC12DJ3200 input. In general, the use of transformers is to provide SE-DE conversion; however, these transformers are inherently band-pass in nature and are not for use in DC-coupled applications. As a result, a common solution is to use a high-speed amplifier to enable DC-coupling without affecting the ADC performance at higher frequencies. Amplifiers offer a flexible and cost-effective solution when the application requires gain, a flat pass-band with low ripple, DC-level shifts, or a DC-coupled signal path. To DC couple the LMH6401 input path, take care to ensure that the common-mode voltage is set within the input common-mode range of the LMH6401 device.

Figure 3-1 shows the design AFE, which is capable of supporting both AC and DC applications for use in a high-performance digital oscilloscope, direct RF input, multichannel radar, and 5G wireless tester. The front-end design consists of a combination of LMH5401 and LMH6401 devices in cascade mode. In the TIDA-01022 reference design, the LMH5401 device is SE-DE configured to accept 50-Ω input signals. The LMH5401 output drives the LMH6401 (DVGA) for the precise gain adjustment which, in turn, drives a fifth-order 2.2-GHz low-pass filter. An ADC (ADC12DJ3200) digitizes the filtered signal output.

GUID-7E0E9EB9-41A9-4639-BEB3-2883D19FE92E-low.gifFigure 3-1 TIDA-01022 AFE

In the first stage of this cascade configuration, the LMH5401 device presents a gain of 4 V/V (12 dB). However, the highest signal bandwidth is 6 GHz in an SE-DE configuration. The 3-dB bandwidth of the LMH6401 is 4.5 GHz, which limits the overall signal bandwidth and allows it to function as a low-pass filter to filter out the harmonics of LMH5401. The LMH6401 gain ranges from –6 dB to 26 dB in 1-dB steps and achieves a 32-dB dynamic range. The LMH6401 device exhibits constant input impedance across the gain setting, which makes it suitable for driving a wideband data converter.

A ±2.5-V dual power supply provides power to both of the LMH5401 and LMH6401 devices. The ADC12DJ3200 requires a zero common-mode input voltage, which the simple resistor divider circuit generates. See the detailed design procedure and calculation for cascaded LMH5401+LMH6401 amplifiers in Cascaded LMH5401 and LMH6401 Reference Design.