TIDUF19 September   2022 ADS1282-SP

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Rset, Rref, and Gain Calculation
      2. 2.2.2 Analog Multiplexer Effect
    3. 2.3 Highlighted Products
      1. 2.3.1 ADS1282-SP
      2. 2.3.2 LMP7704-SP
      3. 2.3.3 TPS7A4501-SP
      4.      16
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Results
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Documentation Support
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author

2.2.1 Rset, Rref, and Gain Calculation

ADS1282-SP input ranges from 0.7 V above AVSS and 1.25 V below AVDD. With AVDD set to 5 V, ADS1282EVM-PDK accepts inputs from 0.7 V to 3.75 V. In TIDA-060042, the Bias Voltage in Figure 2-1 is set to 0.75V. Based on the desired RTD current (IRTD), Rset is calculated with Equation 1.

Equation 1. Rset=0.75 VIRTD

Using the maximum RTD resistance, in this design is 135 Ω, Rref and Gain are calculated with the two formulas (Equation 2 and Equation 3).

Equation 2. Rref>135 Ω ×2×Gain
Equation 3. Rref<5 VIRTD-Rset-135 Ω×10

Once Rset, Rref, and gain are confirmed, the percentage of positive ADC FSR used by each RTD is calculated with Equation 4. For highest performance, Rref is preferred to be as small as possible to maximize the use of positive FSR.

Equation 4. % positive FSR used=135 Ω×2×GainRref×100%