The LMG2100 100V GaN half-bridge power stage provides an integrated and easy-to-use power stage design using enhancement-mode Gallium Nitride (GaN) FETs. The device consists of two GaN FETs driven by one high-frequency GaN FET driver in a half-bridge configuration. The PCB space is further reduced due to high integration and the fact that only a few additional passive components are required. Figure 3-2 shows the schematic of one half-bridge.

Figure 3-2 Half-Bridge Power Stage Schematic for Phase A

The 48V DC-link voltage is connected to the LMG2100 VIN pin and referenced to the power ground (PGND) pin. Local ceramic bypass capacitors C21, C22, C23 (100nF) and C15, C16, C17 (1μF) are placed in parallel close between the VIN and PGND pins to minimize loop inductance.

The LMG2100 integrated gate driver is supplied with 5V. A 2.2μF and 0.1μF ceramic bypass capacitor (C14, C20) are placed close to the VCC pin and AGND pin, as suggested in the data sheet.

Sequencing is not required for the 5V at VCC and the 48V at VIN, neither during the power up or power down of the input DC voltage.

A 100nF ceramic bootstrap capacitors C26 and C27 is placed close to the HB (high-side gate-driver bootstrap rail) and HS (high-side GaN-FET source connection) pins. R5 and R7 are placed to configure the slew rate of the switch node rising edge and related turn-on time. R5 in VCC path can limit the turn-on slew rate of low side GaN-FET and R7 in bootstrap path is for high side GaN-FET. 3Ω was used for the tests in this design for R5 and R7.

The complementary PWM signals for the high-side and low-side switch from the PWM buffer are low-pass filtered with R9, C29 and R11,C31 to reject high-frequency impulse noise and avoid false switching with a cutoff frequency of around 160MHz and a propagation of around 1ns. The SW (switch node) pin is connected to the motor phase-A terminal through a series inline shunt for phase current sensing, and respectively for the other LMG2100R044 half-bridges to the phase B and the phase C terminal.