SBAS773A September   2017  – December 2017 ADS7142

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - All Modes
    6. 6.6  Electrical Characteristics - Manual Mode
    7. 6.7  Electrical Characteristics - Autonomous Modes
    8. 6.8  Electrical Characteristics - High Precision Mode
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics for All Modes
    12. 6.12 Typical Characteristics for Manual Mode
    13. 6.13 Typical Characteristics for Autonomous Modes
    14. 6.14 Typical Characteristics for High Precision Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
        1. 7.3.1.1 Two-Channel, Single-Ended Configuration
        2. 7.3.1.2 Single-Channel, Single-Ended Configuration
        3. 7.3.1.3 Single-Channel, Pseudo-Differential Configuration
      2. 7.3.2  OFFSET Calibration
      3. 7.3.3  Reference
      4. 7.3.4  ADC Transfer Function
      5. 7.3.5  Oscillator and Timing Control
      6. 7.3.6  I2C Address Selector
      7. 7.3.7  Data Buffer
        1. 7.3.7.1 Filling of the Data Buffer
        2. 7.3.7.2 Reading data from the Data Buffer
      8. 7.3.8  Accumulator
      9. 7.3.9  Digital Window Comparator
      10. 7.3.10 I2C Protocol Features
        1. 7.3.10.1 General Call
        2. 7.3.10.2 General Call with Software Reset
        3. 7.3.10.3 General Call with Write Software programmable part of slave address
        4. 7.3.10.4 Configuring Device into High Speed I2C mode
        5. 7.3.10.5 Bus Clear
      11. 7.3.11 Device Programming
        1. 7.3.11.1 Reading Registers
          1. 7.3.11.1.1 Single Register Read
          2. 7.3.11.1.2 Reading a Continuous Block of Registers
        2. 7.3.11.2 Writing Registers
          1. 7.3.11.2.1 Single Register Write
          2. 7.3.11.2.2 Set Bit
          3. 7.3.11.2.3 Clear Bit
          4. 7.3.11.2.4 Writing a continuous block of registers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power Up and Reset
      2. 7.4.2 Manual Mode
        1. 7.4.2.1 Manual Mode with CH0 Only
        2. 7.4.2.2 Manual Mode with AUTO Sequence
      3. 7.4.3 Autonomous Modes
        1. 7.4.3.1 Autonomous Mode with Threshold Monitoring and Diagnostics
          1. 7.4.3.1.1 Autonomous Mode with Pre Alert Data
          2. 7.4.3.1.2 Autonomous Mode with Post Alert Data
        2. 7.4.3.2 Autonomous Mode with Burst Data
          1. 7.4.3.2.1 Autonomous Mode with Start Burst
          2. 7.4.3.2.2 Autonomous Mode with Stop Burst
      4. 7.4.4 High Precision Mode
    5. 7.5 Optimizing Power Consumed by the Device
    6. 7.6 Register Map
      1. 7.6.1 RESET REGISTERS
        1. 7.6.1.1 WKEY Register (address = 17h), [reset = 00h]
        2. 7.6.1.2 DEVICE_RESET Register (address = 14h), [reset = 00h]
      2. 7.6.2 FUNCTIONAL MODE SELECT REGISTERS
        1. 7.6.2.1 OFFSET_CAL Register (address = 15h), [reset = 00h]
        2. 7.6.2.2 OPMODE_SEL Register (address = 1Ch), [reset = 00h]
        3. 7.6.2.3 OPMODE_I2CMODE_STATUS Register (address = 00h), [reset = 00h]
      3. 7.6.3 INPUT CONFIG REGISTER
        1. 7.6.3.1 CHANNEL_INPUT_CFG Register (address = 24h), [reset = 00h]
      4. 7.6.4 ANALOG MUX and SEQUENCER REGISTERS
        1. 7.6.4.1 AUTO_SEQ_CHEN Register (address = 20h), [reset = 03h]
        2. 7.6.4.2 START_SEQUENCE Register (address = 1Eh), [reset = 00h]
        3. 7.6.4.3 ABORT_SEQUENCE Register (address = 1Fh), [reset = 00h]
        4. 7.6.4.4 SEQUENCE_STATUS Register (address = 04h), [reset = 00h]
      5. 7.6.5 OSCILLATOR and TIMING CONTROL REGISTERS
        1. 7.6.5.1 OSC_SEL Register (address = 18h), [reset = 00h]
        2. 7.6.5.2 nCLK_SEL Register (address = 19h), [reset = 00h]
      6. 7.6.6 DATA BUFFER CONTROL REGISTER
        1. 7.6.6.1 DATA_BUFFER_OPMODE Register (address = 2Ch), [reset = 01h]
        2. 7.6.6.2 DOUT_FORMAT_CFG Register (address = 28h), [reset = 00h]
        3. 7.6.6.3 DATA_BUFFER_STATUS Register (address = 01h), [reset = 00h]
      7. 7.6.7 ACCUMULATOR CONTROL REGISTERS
        1. 7.6.7.1 ACC_EN Register (address = 30h), [reset = 00h]
        2. 7.6.7.2 ACC_CH0_LSB Register (address = 08h), [reset = 00h]
        3. 7.6.7.3 ACC_CH0_MSB Register (address = 09h), [reset = 00h]
        4. 7.6.7.4 ACC_CH1_LSB Register (address = 0Ah), [reset = 00h]
        5. 7.6.7.5 ACC_CH1_MSB Register (address = 0Bh), [reset = 00h]
        6. 7.6.7.6 ACCUMULATOR_STATUS Register (address = 02h), [reset = 00h]
      8. 7.6.8 DIGITAL WINDOW COMPARATOR REGISTERS
        1. 7.6.8.1  ALERT_DWC_EN Register (address = 37h), [reset = 00h]
        2. 7.6.8.2  ALERT_CHEN (address = 34h), [reset = 00h]
        3. 7.6.8.3  DWC_HTH_CH0_MSB Register (address = 39h), [reset = 00h]
        4. 7.6.8.4  DWC_HTH_CH0_LSB Register (address = 38h), [reset = 00h]
        5. 7.6.8.5  DWC_LTH_CH0_MSB Register (address = 3Bh), [reset = 00h]
        6. 7.6.8.6  DWC_LTH_CH0_LSB Register (address = 3Ah), [reset = 00h]
        7. 7.6.8.7  DWC_HYS_CH0 (address = 40h), [reset = 00h]
        8. 7.6.8.8  DWC_HTH_CH1_MSB Register (address = 3Dh), [reset = 00h]
        9. 7.6.8.9  DWC_HTH_CH1_LSB Register (address = 3Ch), [reset = 00h]
        10. 7.6.8.10 DWC_LTH_CH1_MSB Register (address = 3Fh), [reset = 00h]
        11. 7.6.8.11 DWC_LTH_CH1_LSB Register (address = 3Eh), [reset = 00h]
        12. 7.6.8.12 DWC_HYS_CH1 (address = 41h), [reset = 00h]
        13. 7.6.8.13 PRE_ALT_MAX_EVENT_COUNT Register (address = 36h), [reset = 00h]
        14. 7.6.8.14 ALERT_TRIG_CHID Register (address = 03h), [reset = 00h]
        15. 7.6.8.15 ALERT_LOW_FLAGS Register (address = 0C), [reset = 00h]
        16. 7.6.8.16 ALERT_HIGH_FLAGS Register (address = 0Eh), [reset = 00h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 ADS7142 as a Programmable Comparator with False Trigger Prevention and Diagnostics
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Higher Power Consumption
          2. 8.2.1.1.2 Fixed Threshold Voltages
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Programmable Thresholds and Hysteresis
          2. 8.2.1.2.2 False Trigger Prevention with Event Counter
          3. 8.2.1.2.3 Fault Diagnostics with Data Buffer
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Event-triggered PIR sensing with ADS7142
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 AVDD and DVDD Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Device and Documentation Support

11.1 Documentation Support

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

11.5 Electrostatic Discharge Caution

esds-image

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.