SLAS986D November 2014  – February 2018 AMC7836

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. PinFunctions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DAC
    6. 6.6 Electrical Characteristics: ADC and Temperature Sensor
    7. 6.7 Electrical Characteristics: General
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics: DAC
    10. 6.10Typical Characteristics: ADC
    11. 6.11Typical Characteristics: Reference
    12. 6.12Typical Characteristics: Temperature Sensor
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Digital-to-Analog Converters (DACs)
        1. 7.3.1.1DAC Output Range and Clamp Configuration
          1. 7.3.1.1.1Auto-Range Detection
        2. 7.3.1.2DAC Register Structure
        3. 7.3.1.3DAC Clear Operation
      2. 7.3.2Analog-to-Digital Converter (ADC)
        1. 7.3.2.1Analog Inputs
          1. 7.3.2.1.1Bipolar Analog Inputs
          2. 7.3.2.1.2Unipolar Analog Inputs
        2. 7.3.2.2ADC Sequencing
        3. 7.3.2.3ADC Synchronization
        4. 7.3.2.4Programmable Out-of-Range Alarms
          1. 7.3.2.4.1Unipolar Inputs Out-of-Range Alarms
          2. 7.3.2.4.2Unipolar Inputs Out-of-Range Alarms
          3. 7.3.2.4.3ALARMIN Alarm
          4. 7.3.2.4.4Hysteresis
          5. 7.3.2.4.5False-Alarm Protection
      3. 7.3.3Internal Temperature Sensor
      4. 7.3.4Internal Reference
      5. 7.3.5General Purpose I/Os
    4. 7.4Device Functional Modes
      1. 7.4.1All-Positive DAC Range Mode
      2. 7.4.2All-Negative DAC Range Mode
      3. 7.4.3Mixed DAC Range Mode
    5. 7.5Programming
    6. 7.6Register Maps
      1. 7.6.1 Interface Configuration: Address 0x00 – 0x02
        1. 7.6.1.1Interface Configuration 0 Register (address = 0x00) [reset = 0x30]
          1. Table9. Interface Config 0 Register Field Descriptions (R/W)
        2. 7.6.1.2Interface Configuration 1 Register (address = 0x01) [reset = 0x00]
          1. Table10. Interface Config 1 Register Field Descriptions
        3. 7.6.1.3Device Configuration Register (address = 0x02) [reset = 0x03]
          1. Table11. Device Config Register Field Descriptions
      2. 7.6.2 Device Identification: Address 0x03 – 0x0D
        1. 7.6.2.1Chip Type Register (address = 0x03) [reset = 0x08]
          1. Table12. Chip Type Register Field Descriptions
        2. 7.6.2.2Chip ID Low Byte Register (address = 0x04) [reset = 0x36]
          1. Table13. Chip ID Low Byte Register Field Descriptions
        3. 7.6.2.3Chip ID High Byte Register (address = 0x05) [reset = 0x0C]
          1. Table14. Chip ID High Byte Register Field Descriptions
        4. 7.6.2.4Version ID Register (address = 0x06) [reset = 0x00]
          1. Table15. Version ID Register Field Descriptions
        5. 7.6.2.5Manufacturer ID Low Byte Register (address = 0x0C) [reset = 0x51]
          1. Table16. Manufacturer ID Low Byte Register Field Descriptions
        6. 7.6.2.6Manufacturer ID High Byte Register (address = 0x0D) [reset = 0x04]
          1. Table17. Manufacturer ID High Byte Register Field Descriptions
      3. 7.6.3 Register Update (Buffered Registers): Address 0x0F
        1. 7.6.3.1Register Update Register (address = 0x0F) [reset = 0x00]
          1. Table18. Register Update Register Field Descriptions
      4. 7.6.4 General Device Configuration: Address 0x10 through 0x17
        1. 7.6.4.1ADC Configuration Register (address = 0x10) [reset = 0x00]
          1. Table19. ADC Configuration Register Field Descriptions
        2. 7.6.4.2False Alarm Configuration Register (address = 0x11) [reset = 0x70]
          1. Table21. False Alarm Configuration Register Field Descriptions
        3. 7.6.4.3GPIO Configuration Register (address = 0x12) [reset = 0x00]
          1. Table24. GPIO Configuration Register Field Descriptions
        4. 7.6.4.4ADC MUX Configuration 0 Register (address = 0x13) [reset = 0x00]
          1. Table25. ADC MUX Configuration 0 Register Field Descriptions
        5. 7.6.4.5ADC MUX Configuration 1 Register (address = 0x14) [reset = 0x00]
          1. Table26. ADC MUX Configuration 1 Register Field Descriptions
        6. 7.6.4.6ADC MUX Configuration 2 Register (address = 0x15) [reset = 0x00]
          1. Table27. ADC MUX Configuration 2 Register Field Descriptions
        7. 7.6.4.7DAC Clear Enable 0 Register (address = 0x18) [reset = 0x00]
          1. Table28. DAC Clear Enable 0 Register Field Descriptions
        8. 7.6.4.8DAC Clear Enable 1 Register (address = 0x19) [reset = 0x00]
          1. Table29. DAC Clear Enable 1 Register Field Descriptions
      5. 7.6.5 DAC Clear and ALARMOUT Source Select: Address 0x1A through 0x1D
        1. 7.6.5.1DAC Clear Source 0 Register (address = 0x1A) [reset = 0x00]
          1. Table30. DAC Clear Source 0 Register Field Descriptions
        2. 7.6.5.2DAC Clear Source 1 Register (address = 0x1B) [reset = 0x00]
          1. Table31. DAC Clear Source 1 Register Field Descriptions
        3. 7.6.5.3ALARMOUT Source 0 Register (address = 0x1c) [reset = 0x00]
          1. Table32. ALARMOUT Source 0 Register Field Descriptions
        4. 7.6.5.4ALARMOUT Source 1 Register (address = 0x1D) [reset = 0x00]
          1. Table33. ALARMOUT Source 1 Register Field Descriptions
      6. 7.6.6 DAC Range: Address 0x1E
        1. 7.6.6.1DAC Range Register (address = 0x1E) [reset = 0x00]
          1. Table34. DAC Range Register Field Descriptions
        2. 7.6.6.2DAC Range 1 Register (address = 0x1F) [reset = 0x00]
          1. Table36. DAC Range 1 Register Field Descriptions
      7. 7.6.7 ADC and Temperature Data: Address 0x20 through 0x4B
        1. 7.6.7.1ADCn-Data (Low Byte) Register (address = 0x20 through 0x49) [reset = 0x00]
          1. Table37. ADCn-Data (Low Byte) Register Field Descriptions
        2. 7.6.7.2ADCn-Data (High Byte) Register (address = 0x20 through 0x49) [reset = 0x00]
          1. Table38. ADCn-Data (High Byte) Register Field Descriptions
        3. 7.6.7.3Temperature Data (Low Byte) Register (address = 0x4A) [reset = 0x00]
          1. Table39. Temperature Data (Low Byte) Register Field Descriptions
        4. 7.6.7.4Temperature Data (High Byte) Register (address = 0x4B) [reset = 0x00]
          1. Table40. Temperature Data (High Byte) Register Field Descriptions
      8. 7.6.8 DAC Data: Address 0x50 through 0x6F
        1. 7.6.8.1DACn-Data (Low Byte) Register (address = 0x50 through 0x6F) [reset = 0x00]
          1. Table41. DACn-Data (Low Byte) Register Field Descriptions
        2. 7.6.8.2DACn Data (High Byte) Register (address = 0x50 through 0x6F) [reset = 0x00]
          1. Table42. DACn Data (High Byte) Register Field Descriptions
      9. 7.6.9 Status Registers: Address 0x70 through 0x72
        1. 7.6.9.1Alarm Status 0 Register (address = 0x70) [reset = 0x00]
          1. Table43. Alarm Status 0 Register Field Descriptions
        2. 7.6.9.2Alarm Status 1 Register (address = 0x71) [reset = 0x00]
          1. Table44. Alarm Status 1 Register Field Descriptions
        3. 7.6.9.3General Status Register (address = 0x72) [reset = 0x0C]
          1. Table45. General Status Register Field Descriptions
      10. 7.6.10GPIO: Address 0x7A
        1. 7.6.10.1GPIO Register (address = 0x7A) [reset = 0xFF]
          1. Table46. GPIO Register Field Descriptions
      11. 7.6.11Out-Of-Range ADC Thresholds: Address 0x80 through 0x93
        1. 7.6.11.1ADCn-Upper-Thresh (Low Byte) Register (address = 0x80 through 0x93) [reset = 0xFF]
          1. Table47. ADCn-Upper-Thresh (Low Byte) Register Field Descriptions
        2. 7.6.11.2ADCn-Upper-Thresh (High Byte) Register (address = 0x80 through 0x93) [reset = 0x0F]
          1. Table48. ADCn-Upper-Thresh (High Byte) Register Field Descriptions
        3. 7.6.11.3ADCn-Lower-Thresh (Low Byte) Register (address = 0x80 through 0x93) [reset = 0x00]
          1. Table49. ADCn-Lower-Thresh (Low Byte) Register Field Descriptions
        4. 7.6.11.4ADCn-Lower-Thresh (High Byte) Register (address = 0x80 through 0x93) [reset = 0x00]
          1. Table50. ADCn-Lower-Thresh (High Byte) Register Field Descriptions Field Descriptions
        5. 7.6.11.5LT-Upper-Thresh (Low Byte) Register (address = 0x94) [reset = 0xFF]
          1. Table51. LT-Upper-Thresh (Low Byte) Register Field Descriptions
        6. 7.6.11.6LT-Upper-Thresh (High Byte) Register (address = 0x95) [reset = 0x07]
          1. Table52. LT-Upper-Thresh (High Byte) Register Field Descriptions
        7. 7.6.11.7LT-Lower-Thresh (Low Byte) Register (address = 0x96) [reset = 0x00]
          1. Table53. LT-Lower-Thresh (Low Byte) Register Field Descriptions
        8. 7.6.11.8LT-Lower-Thresh (High Byte) Register (address = 0x97) [reset = 0x08]
          1. Table54. LT-Lower-Thresh (High Byte) Register Field Descriptions
      12. 7.6.12Alarm Hysteresis Configuration: Address 0xA0 and 0xA5
        1. 7.6.12.1ADCn-Hysteresis Register (address = 0xA0 through 0xA4) [reset = 0x08]
          1. Table55. ADCn-Hysteresis Register Field Descriptions
        2. 7.6.12.2LT-Hysteresis Register (address = 0xA5) [reset = 0x08]
          1. Table56. LT-Hysteresis Register Field Descriptions
      13. 7.6.13Clear and Power-Down Registers: Address 0xB0 through 0XB4
        1. 7.6.13.1DAC Clear 0 Register (address = 0xB0) [reset = 0x00]
          1. Table57. DAC Clear 0 Register Field Descriptions
        2. 7.6.13.2DAC Clear 1 Register (address = 0xB1) [reset = 0x00]
          1. Table58. DAC Clear 1 Register Field Descriptions
        3. 7.6.13.3Power-Down 0 Register (address = 0xB2) [reset = 0x00]
          1. Table59. Power-Down 0 Register Field Descriptions
        4. 7.6.13.4Power-Down 1 Register (address = 0xB3) [reset = 0x00]
          1. Table60. Power-Down 1 Register Field Descriptions
        5. 7.6.13.5Power-Down 2 Register (address = 0xB4) [reset = 0x00]
          1. Table61. Power-Down 2 Register Field Descriptions
      14. 7.6.14ADC Trigger: Address 0xC0
        1. 7.6.14.1ADC Trigger Register (address = 0xC0) [reset = 0x00]
          1. Table62. ADC Trigger Register Field Descriptions
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Temperature Sensing Applications
      2. 8.1.2Current Sensing Applications
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
        1. 8.2.2.1ADC Input Conditioning
        2. 8.2.2.2DAC Output Range Selection
      3. 8.2.3Application Curves
  9. Power Supply Recommendations
    1. 9.1Device Reset Options
      1. 9.1.1Power-on-Reset (POR)
      2. 9.1.2Hardware Reset
        1. 9.1.2.1Software Reset
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
    2. 11.2Receiving Notification of Documentation Updates
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Mechanical Data (Package|Pins)
Orderable Information