SLUSBU9D March 2014  – May 2016

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Configurations
  6. Pin Configuration and Functions
    1. 6.1Pin Descriptions
      1. 6.1.1Supply Input: BAT
      2. 6.1.2Cell Negative Connection: VSS
      3. 6.1.3Voltage Sense Node: V-
      4. 6.1.4Discharge FET Gate Drive Output: DOUT
      5. 6.1.5Charge FET Gate Drive Output: COUT
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5DC Characteristics
    6. 7.6Programmable Fault Detection Thresholds
    7. 7.7Programmable Fault Detection Timer Ranges
    8. 7.8Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1Timing Charts
    2. 8.2Test Circuits
    3. 8.3Test Circuit Diagrams
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
    4. 9.4Device Functional Modes
      1. 9.4.1Normal Operation
      2. 9.4.2Overcharge Status
      3. 9.4.3Over-Discharge Status
      4. 9.4.4Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)
      5. 9.4.5Charge Overcurrent Status
      6. 9.4.60-V Charging Function (Available)
      7. 9.4.70-V Charging Function (Unavailable)
      8. 9.4.8Delay Circuit
  10. 10Applications and Implementation
    1. 10.1Application Information
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
      3. 10.2.3Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Related Links
    2. 13.2Community Resources
    3. 13.3Trademarks
    4. 13.4Electrostatic Discharge Caution
    5. 13.5Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MINMAXUNIT
Supply control and inputInput voltage: BAT–0.312V
V– pin(pack–)BAT – 28BAT + 0.3V
FET drive and protectionDOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive)VSS – 0.3BAT + 0.3V
COUT (Charge FET Output), GCHG (Charge FET Gate Drive)BAT – 28BAT + 0.3V
Operating temperature: TFUNC–4085°C
Storage temperature, Tstg –55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

7.2 ESD Ratings

VALUEUNIT
VESD(1) Electrostatic DischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2)±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3)±500
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V can have higher performance.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V can have higher performance.

7.3 Recommended Operating Conditions(1)

MINMAXUNIT
Supply control and inputPositive input voltage: BAT–0.38V
Negative input voltage: V– BAT – 25BAT V
FET drive and protectionDischarge FET control: DOUTVSSBAT V
Charge FET control: COUTBAT – 25BAT V
Temperature RatingsOperating temperature: TAmb –4085°C
Storage temperature: TS–55150°C
Lead temperature (soldering 10 s)300°C
Thermal resistance junction to ambient, θJA(1)250°C/W
(1) For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1)bq297xxUNIT
DSE (WSON)
12 PINS
RθJA, High KJunction-to-ambient thermal resistance(2) 190.5°C/W
RθJC(top)Junction-to-case(top) thermal resistance(3) 94.9°C/W
RθJBJunction-to-board thermal resistance(4) 149.3°C/W
ψJTJunction-to-top characterization parameter(5) 6.4°C/W
ψJBJunction-to-board characterization parameter(6) 152.8°C/W
RθJC(bottom)Junction-to-case(bottom) thermal resistance(7) N/A°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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7.5 DC Characteristics

Typical Values stated where TA = 25°C and BAT = 3.6 V. Min/Max values stated where TA = –40°C to 85°C, and BAT = 3 V to 4.2 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Current consumption
VBATDevice operating rangeBAT – VSS1.58V
BAT – V–1.528
INORMALCurrent consumption in NORMAL modeBAT = 3.8 V, V– = 0 V45.5µA
IPower_downCurrent consumption in power down modeBAT = V– = 1.5 V0.1µA
FET Output, DOUT and COUT
VOLCharge FET low outputIOL = 30 µA, BAT = 3.8 V0.40.5V
VOHCharge FET high outputIOH = –30 µA, BAT = 3.8 V3.43.7V
VOLDischarge FET low outputIOL = 30 µA, BAT = 2 V0.20.5V
VOHDischarge FET high outputIOH = –30 µA, BAT = 3.8 V3.43.7V
Pullup Internal Resistance on V–
RV–DResistance between V– and VBATVBAT = 1.8 V, V– = 0 V100300550
Current sink on V–
IV–SCurrent sink on V– to VSSVBAT = 3.8 V824µA
Load short detection on V–
VshortShort detection voltageVBAT = 3.8 V and RPackN = 2.2 kΩVBAT – 1 VV
0-V battery charge function
V0CHG0-V battery charging starter voltage0-V battery charging function allowed1.7V
V0INH0-V battery charging inhibit voltage0-V battery charging function disallowed0.75V

7.6 Programmable Fault Detection Thresholds

PARAMETERCONDITIONMINTYPMAXUNIT
VOVPOvercharge detection voltage Factory Device Configuration: 3.85 V to 4.60 V in 50-mV steps TA = 25°C–10 10mV
TA = 0°C to 60°C–2020mV
VOVP–HysOvercharge release hysteresis voltage 100 mV and (VSS – V–) > OCC (min) for release, TA = 25°C–2020mV
VUVPOver-discharge detection voltageFactory Device Configuration: 2.00 V to 2.80 V in 50-mV steps, TA = 25°C–5050mV
VUVP+HysOver-discharge release hysteresis voltage 100 mV and (BAT – V–) > 1 V for release, TA = 25°C–50 50mV
VOCDDischarging overcurrent detection voltage Factory Device Configuration: 90 mV to 200 mV in 5-mV stepsTA = 25°C–10 10mV
TA = –40°C to 85°C–1515mV
Release of VOCDRelease of discharging overcurrent detection voltage Release when BAT – V– > 1 V1V
VOCCCharging overcurrent detection voltage Factory Device Configuration: –45 mV to –155 mV in 5-mV stepsTA = 25°C–10 10mV
TA = –40°C to 85°C–1515mV
Release of VOCCRelease of overcurrent detection voltageRelease when VSS – V– ≥ OCC (min)40 mV
VSCCShort Circuit detection voltageFactory Device Configuration: 300 mV, 400 mV, 500 mV, 600 mV TA = 25°C–100100mV
VSCCRRelease of Short Circuit detection voltage Release when BAT – V– ≥ 1 V1 V

7.7 Programmable Fault Detection Timer Ranges

PARAMETER CONDITION MIN TYPMAXUNIT
tOVPDOvercharge detection delay timeFactory Device Configuration: 0.25 s, 1 s, 1.25 s, 4.5 s –20%20%s
tUVPDOver-discharge detection delay timeFactory Device Configuration: 20 ms, 96 ms, 125 ms, 144 ms –20% 20%ms
tOCDDDischarging overcurrent detection delay timeFactory Device Configuration: 8 ms, 16 ms, 20 ms, 48 ms –20%20%ms
tOCCDCharging overcurrent detection delay timeFactory Device Configuration: 4 ms, 6 ms, 8 ms, 16 ms –20%20%ms
tSCCDShort Circuit detection delay time 250 µs (fixed)–50%50%µs

7.8 Typical Characteristics

bq2970 bq2971 bq2972 bq2973 C001_IBAT_1p5V_SLUSBU9.png
VBAT = 1.5 V
Figure 1. 1.5-V IBAT Versus Temperature
bq2970 bq2971 bq2972 bq2973 C003_INT_OSC_SLUSBU9.png
FOSC, Setting = 1.255 kHz
Figure 3. Internal Oscillator Frequency Versus Temperature
bq2970 bq2971 bq2972 bq2973 C005_0V_DISALLOWED_SLUSBU9.png
Figure 5. 0-V Charging Disallowed Versus Temperature
bq2970 bq2971 bq2972 bq2973 C007_OVP_DET_DEL_SLUSBU9.png
tOVPD, Setting = 1.25 s
Figure 7. OVP Detection Dely Time Versus Temperature
bq2970 bq2971 bq2972 bq2973 C009_UVP_DET_DEL_SLUSBU9.png
tUVPD, Setting = 144 ms
Figure 9. UVP Detection Delay Time Versus Temperature
bq2970 bq2971 bq2972 bq2973 C011_OCC_DET_DEL_SLUSBU9.png
tOCCD, Setting = 8 ms
Figure 11. OCC Detection Delay Time Versus Temperature
bq2970 bq2971 bq2972 bq2973 C013_OCD_DET_DEL_SLUSBU9.png
tUVPD, Setting = 20 ms
Figure 13. OCD Detection Delay Time Versus Temperature
bq2970 bq2971 bq2972 bq2973 C015_PWR_ON_RESET_SLUSBU9.png
Figure 15. Power On Reset Versus Temperature
bq2970 bq2971 bq2972 bq2973 C017_DOUT_SLUSBU9.png
VBAT, Setting = 3.9 V
Figure 17. DOUT Versus Temperature with Ioh = –30 µA
bq2970 bq2971 bq2972 bq2973 C002_IBAT_3p9V_SLUSBU9.png
VBAT = 3.9 V
Figure 2. 3.9-V IBAT Versus Temperature
bq2970 bq2971 bq2972 bq2973 C004_0V_ALLOWED_SLUSBU9.png
VBAT, Setting = 0 V
Figure 4. 0-V Charging Allowed Versus Temperature
bq2970 bq2971 bq2972 bq2973 C006_OVP_DET_ACC_SLUSBU9.png
OVP, Setting = 4.275 V
Figure 6. OVP Detection Accuracy Versus Temperature
bq2970 bq2971 bq2972 bq2973 C008_UVP_DET_ACC_SLUSBU9.png
UVP, Setting = 2.800 V
Figure 8. UVP Detection Accuracy Versus Temperature
bq2970 bq2971 bq2972 bq2973 C010_OCC_DET_ACC_SLUSBU9.png
VOCC, Setting = –100 mV
Figure 10. OCC Detection Accuracy Versus Temperature
bq2970 bq2971 bq2972 bq2973 C012_OCD_DET_ACC_SLUSBU9.png
VOCD, Setting = 100 mV
Figure 12. OCD Detection Accuracy Versus Temperature
bq2970 bq2971 bq2972 bq2973 C014_SCC_DET_ACC_SLUSBU9.png
VSCC, Setting = 500 mV
Figure 14. SCC Detection Accuracy Versus Temperature
bq2970 bq2971 bq2972 bq2973 C016_COUT_SLUSBU9.png
VBAT, Setting = 3.9 V
Figure 16. COUT Versus Temperature with Ioh = –30 µA