DLPS029F April 2013 – May 2019 DLPC350
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | FROM (INPUT) | TO (OUTPUT) | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|---|
ƒclock1 | Clock frequency(1)(2) | N/A | DMD_DCLK | 79.992 | 120.012 | MHz | |
tp1_clkper | Clock period | 50% reference points | N/A | DMD_DCLK | 8.332 | 12.502 | ns |
tp1_cwh | Clock pulse duration low | 50% reference points | N/A | DMD_DCLK | 3.75 | ns | |
tp1_cwl | Clock pulse duration high | 50% reference points | N/A | DMD_DCLK | 3.75 | ns | |
ƒclock2 | Clock frequency(2) | N/A | DMD_SAC_CLK | 74.659 | 74.675 | MHz | |
tp2_clkper | Clock period | 50% reference points | N/A | DMD_SAC_CLK | 13.391 | 13.394 | ns |
tp2_cwh | Clock pulse duration low | 50% reference points | N/A | DMD_SAC_CLK | 6 | ns | |
tp2_cwl | Clock pulse duration high | 50% reference points | N/A | DMD_SAC_CLK | 6 | ns | |
tslew | Slew rate(3)(4)(5) | N/A | All | 0.7 | V/ns | ||
tp1_su | Output setup time(6) | 50% reference points | Both rising and falling edges of DMD_DCLK | DMD_D(23:0), DMD_SCTRL, DMD_LOADB, DMD_TRC | 1.10 | ns | |
tp1_h | Output hold time(6) | 50% reference points | Both rising and falling edges of DMD_DCLK | DMD_D(23:0), DMD_SCTRL, DMD_LOADB, DMD_TRC | 1.10 | ns | |
tp1_skew | DMD data skew | 50% reference points | Relative to each other | DMD_D(23:0), DMD_SCTRL, DMD_LOADB, DMD_TRC, DMD_DCLK | 0.2 | ns | |
tp2_su | Output setup time(6) | 50% reference points | Rising edge of DMD_SAC_CLK | DMD_SAC_BUS, DMD_DRC_OE, DMD_DRC_BUS, DMD_DRC_STRB | 2.35 | ns | |
tp2_h | Output hold time(6) | 50% reference points | Rising edge of DMD_SAC_CLK | DMD_SAC_BUS, DMD_DRC_OE, DMD_DRC_BUS, DMD_DRC_STRB | 2.35 | ||
tp2_skew | DRC/SAC data skew | 50% reference points | Relative to each other | DMD_SAC_BUS, DMD_DRC_OE, DMD_DRC_BUS, DMD_DRC_STRB, DMD_SAC_CLK | 0.2 | ns |