SLASEB7B June 2017  – December 2017 MSP430FR6047

PRODUCTION DATA. 

  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1Pin Diagram
    2. 4.2Pin Attributes
    3. 4.3Signal Descriptions
    4. 4.4Pin Multiplexing
    5. 4.5Buffer Type
    6. 4.6Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Typical Characteristics, Active Mode Supply Currents
    6. 5.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11Typical Characteristics, Current Consumption per Module
    12. 5.12Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
      2. 5.13.2 Reset Timing
      3. 5.13.3 Clock Specifications
      4. 5.13.4 Wake-up Characteristics
        1. 5.13.4.1Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5 Digital I/Os
        1. 5.13.5.1Typical Characteristics, Digital Outputs
      6. 5.13.6 LEA
      7. 5.13.7 Timer_A and Timer_B
      8. 5.13.8 eUSCI
      9. 5.13.9 Segment LCD Controller
      10. 5.13.10ADC12_B
      11. 5.13.11Reference
      12. 5.13.12Comparator
      13. 5.13.13FRAM
      14. 5.13.14USS
      15. 5.13.15Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 CPU
    3. 6.3 Ultrasonic Sensing Solution (USS) Module
    4. 6.4 Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5 Operating Modes
      1. 6.5.1Peripherals in Low-Power Modes
      2. 6.5.2Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6 Interrupt Vector Table and Signatures
    7. 6.7 Bootloader (BSL)
    8. 6.8 JTAG Operation
      1. 6.8.1JTAG Standard Interface
      2. 6.8.2Spy-Bi-Wire (SBW) Interface
    9. 6.9 FRAM Controller A (FRCTL_A)
    10. 6.10RAM
    11. 6.11Tiny RAM
    12. 6.12Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13Peripherals
      1. 6.13.1 Digital I/O
      2. 6.13.2 Oscillator and Clock System (CS)
      3. 6.13.3 Power-Management Module (PMM)
      4. 6.13.4 Hardware Multiplier (MPY)
      5. 6.13.5 Real-Time Clock (RTC_C)
      6. 6.13.6 Measurement Test Interface (MTIF)
      7. 6.13.7 Watchdog Timer (WDT_A)
      8. 6.13.8 System Module (SYS)
      9. 6.13.9 DMA Controller
      10. 6.13.10Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11TA0, TA1, and TA4
      12. 6.13.12TA2 and TA3
      13. 6.13.13TB0
      14. 6.13.14ADC12_B
      15. 6.13.15USS
      16. 6.13.16Comparator_E
      17. 6.13.17CRC16
      18. 6.13.18CRC32
      19. 6.13.19AES256 Accelerator
      20. 6.13.20True Random Seed
      21. 6.13.21Shared Reference (REF)
      22. 6.13.22LCD_C
      23. 6.13.23Embedded Emulation
        1. 6.13.23.1Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2EnergyTrace++ Technology
    14. 6.14Input/Output Diagrams
      1. 6.14.1 Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9 Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15Device Descriptors (TLV)
    16. 6.16Memory Map
      1. 6.16.1Peripheral File Map
    17. 6.17Identification
      1. 6.17.1Revision Identification
      2. 6.17.2Device Identification
      3. 6.17.3JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator (HFXT and LFXT)
      3. 7.1.3 USS Oscillator (USSXT)
      4. 7.1.4 Transducer Connection to the USS Module
      5. 7.1.5 Charge Pump Control of Input Multiplexer
      6. 7.1.6 JTAG
      7. 7.1.7 Reset
      8. 7.1.8 Unused Pins
      9. 7.1.9 General Layout Recommendations
      10. 7.1.10Do's and Don'ts
    2. 7.2Peripheral- and Interface-Specific Design Information
      1. 7.2.1ADC12_B Peripheral
        1. 7.2.1.1Partial Schematic
        2. 7.2.1.2Design Requirements
        3. 7.2.1.3Detailed Design Procedure
        4. 7.2.1.4Layout Guidelines
      2. 7.2.2LCD_C Peripheral
        1. 7.2.2.1Partial Schematic
        2. 7.2.2.2Design Requirements
        3. 7.2.2.3Detailed Design Procedure
        4. 7.2.2.4Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1Getting Started and Next Steps
    2. 8.2Device and Development Tool Nomenclature
    3. 8.3Tools and Software
    4. 8.4Documentation Support
    5. 8.5Related Links
    6. 8.6Trademarks
    7. 8.7Electrostatic Discharge Caution
    8. 8.8Export Control Notice
    9. 8.9Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Device Overview

Features

  • Best-in-Class Ultrasonic Water-Flow Measurement With Ultra-Low Power Consumption
    • <25-ps Differential Time-of-Flight (dTOF) Accuracy
    • High-Precision Time Measurement Resolution of <5 ps
    • Ability to Detect Low Flow Rates (<1 Liter per Hour)
    • Approximately 3-µA Overall Current Consumption With One Measurement per Second
  • Compliant to and Exceeds ISO 4064, OIML R49, and EN 1434 Accuracy Standards
  • Ability to Directly Interface Standard Ultrasonic Sensors (up to 2.5 MHz)
  • Integrated Analog Front End – Ultrasonic Sensing Solution (USS)
    • Programmable Pulse Generation (PPG) to Generate Pulses at Different Frequencies
    • Integrated Physical Interface (PHY) With Low-Impedance (4-Ω) Output Driver to Control Input and Output Channels
    • High-Performance High-Speed 12-Bit Sigma-Delta ADC (SDHS) With Output Data Rates up to 8 Msps
    • Programmable Gain Amplifier (PGA) With –6.5 dB to 30.8 dB
    • High-Performance Phase-Locked Loop (PLL) With Output Range of 68 MHz to 80 MHz
  • Metering Test Interface (MTIF)
    • Pulse Generator and Pulse Counter
    • Pulse Rates up to 1016 Pulses per Second (p/s)
    • Count Capacity up to 65535 (16 Bit)
    • Operates in LPM3.5 With 200 nA (Typical)
  • Low-Energy Accelerator (LEA)
    • Operation Independent of CPU
    • 4KB of RAM Shared With CPU
    • Efficient 256-Point Complex FFT:
      Up to 40× Faster Than Arm® Cortex®-M0+ Core
  • Embedded Microcontroller
    • 16-Bit RISC Architecture up to 16‑MHz Clock
    • Wide Supply Voltage Range:
      1.8 V to 3.6 V (1)
  • Optimized Ultra-Low-Power Modes
    • Active Mode: Approximately 120 µA/MHz
    • Standby Mode With Real-Time Clock (RTC) (LPM3.5): 450 nA (2)
    • Shutdown (LPM4.5): 30 nA
  • Ferroelectric Random Access Memory (FRAM)
    • Up to 256KB of Nonvolatile Memory
    • Ultra-Low-Power Writes
    • Fast Write at 125 ns Per Word (64KB in 4 ms)
    • Unified Memory = Program + Data + Storage in One Space
    • 1015 Write Cycle Endurance
    • Radiation Resistant and Nonmagnetic
  • Intelligent Digital Peripherals
    • 32-Bit Hardware Multiplier (MPY)
    • 6-Channel Internal DMA
    • RTC With Calendar and Alarm Functions
    • Six 16-Bit Timers With up to Seven Capture/Compare Registers Each
    • 32-Bit and 16-Bit Cyclic Redundancy Check (CRC)
  • High-Performance Analog
    • 16-Channel Analog Comparator
    • 12-Bit SAR ADC Featuring Window Comparator, Internal Reference, and Sample-and-Hold, up to 16 External Input Channels
    • Integrated LCD Driver With Contrast Control for up to 264 Segments
  • Multifunction Input/Output Ports
    • Accessible Bit-, Byte-, and Word-Wise (in Pairs)
    • Edge-Selectable Wake From LPM on All Ports
    • Programmable Pullup and Pulldown on All Ports
  • Code Security and Encryption
    • 128- or 256-Bit AES Security Encryption and Decryption Coprocessor
    • Random Number Seed for Random Number Generation Algorithms
    • IP Encapsulation Protects Memory From External Access
    • FRAM Provides Inherent Security Advantages
  • Enhanced Serial Communication
    • Up to Four eUSCI_A Serial Communication Ports
      • UART With Automatic Baud-Rate Detection
      • IrDA Encode and Decode
    • Up to Two eUSCI_B Serial Communication Ports
      • I2C With Multiple-Slave Addressing
    • Hardware UART or I2C Bootloader (BSL)
  • Flexible Clock System
    • Fixed-Frequency DCO With 10 Selectable Factory-Trimmed Frequencies
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • 32-kHz Crystals (LFXT)
    • High-Frequency Crystals (HFXT)
  • Development Tools and Software (Also See Tools and Software)
  • Device Comparison Summarizes the Available Device Variants and Package Options
  • For Complete Module Descriptions, See the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide
Minimum supply voltage is restricted by SVS levels.The RTC is clocked by a 3.7-pF crystal.
The RTC is clocked by a 3.7-pF crystal.
Minimum supply voltage is restricted by SVS levels.

Applications

  • Ultrasonic Smart Water Meters
  • Ultrasonic Smart Heat Meters
  • Liquid Level Sensing
  • Water Leak Detection

Description

The Texas Instruments MSP430FR604x and MSP430FR603x family of ultrasonic sensing and measurement SoCs are powerful, highly integrated microcontrollers (MCUs) that are optimized for water and heat meters. The MSP430FR604x MCUs offer an integrated Ultrasonic Sensing Solution (USS) module, which provides high accuracy for a wide range of flow rates. The USS module helps achieve ultra-low-power metering combined with lower system cost due to maximum integration requiring very few external components. MSP430FR604x and MSP430FR603x MCUs implement a high-speed ADC-based signal acquisition followed by optimized digital signal processing using the integrated Low-Energy Accelerator (LEA) module to deliver a high-accuracy metering solution with ultra-low power optimum for battery-powered metering applications.

The USS module includes a programmable pulse generator (PPG) and a physical interface (PHY) with a low-impedance output driver for optimum sensor excitation and accurate impendence matching to deliver best results for zero-flow drift (ZFD). The module also includes a programmable gain amplifier (PGA) and a high-speed 12-bit 8-Msps sigma-delta ADC (SDHS) for accurate signal acquisition from industry-standard ultrasonic transducers.

Additionally, MSP430FR604x and MSP430FR603x MCUs integrate other peripherals to improve system integration for metering. The devices have a metering test interface (MTIF) module to implement pulse generation to indicate flow measured by the meter. The MSP430FR604x and MSP430FR603x MCUs also have an on-chip 8-mux LCD driver, an RTC, a 12-bit SAR ADC, an analog comparator, an advanced encryption accelerator (AES256), and a cyclic redundancy check (CRC) module.

MSP430FR604x and MSP430FR603x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. Development kits include the MSP-TS430PZ100E 100-pin target development board and EVM430-FR6047 ultrasonic water flow meter EVM. TI also provides free software including the ultrasonic sensing design center, ultrasonic sensing software library, and MSP430Ware software.

TI's MSP430 ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a holistic ultra-low-power system architecture, letting system designers increase performance while lowering energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM with the nonvolatility of flash.

Device Information(1)(2)

PART NUMBERPACKAGEBODY SIZE(3)
MSP430FR6047IPZ
MSP430FR60471IPZ
MSP430FR6045IPZ
MSP430FR6037IPZ
MSP430FR60371IPZ
MSP430FR6035IPZ
LQFP (100)14 mm × 14 mm
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
For a comparison of all available device variants, see Section 3.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

Functional Block Diagrams

Figure 1-1 and Figure 1-2 show the functional block diagrams of the devices.

MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 msp430fr6047-functional-block-diagram.gif

NOTE:

The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 1-1 MSP430FR604x Functional Block Diagram
MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 bd_FR603xNoPo.gif

NOTE:

The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem.
Figure 1-2 MSP430FR603x Functional Block Diagram