Inicio Microcontroladores (MCU) y procesadores Procesadores basados en Arm
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Microcontroladores (MCU) y procesadores
Procesadores basados en Arm

DRA745

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Procesador ARM Cortex-A15 SoC de 1.2 GHz doble con gráficos y DSP para información y entretenimiento

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DRA745

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Detalles del producto

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1176 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1176 Coprocessors 2 Dual Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100/1000, 2-Port 1Gb switch PCIe 1 PCIe Gen 2 Hardware accelerators 1 Image Video Accelerator, 2 Viterbi Decoder, Audio Tracking Features Multimedia Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.
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Más información

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Documentación técnica

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Tipo Título Fecha
* Data sheet DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 07 may 2019
* Errata DRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. J) PDF | HTML 08 ene 2021
Application note Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05 may 2021
Application note IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24 ago 2020
User guide DRA75x, DRA74x Technical Reference Manual (SR2.0 & SR1.1) (Rev. G) 21 feb 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 ene 2020
Application note Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11 jun 2019
Application note Achieving Early CAN Response on DRA7xx Devices 28 nov 2018
Application note DRA74x_75x/DRA72x Performance (Rev. A) 31 oct 2018
Application note Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14 sep 2018
Application note The Implementation of YUV422 Output for SRV 02 ago 2018
Application note MMC DLL Tuning (Rev. B) 31 jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 jun 2018
Application note Tools and Techniques to Root Case Failures in Video Capture Subsystem 12 jun 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 may 2018
Application note Android Boot Optimization on DRA7xx Devices (Rev. A) 13 feb 2018
Application note Flashing Utility - mflash 09 ene 2018
Application note Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30 nov 2017
Application note Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 27 nov 2017
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 nov 2017
Application note Robust Rear-View Camera (RVC) App Report 13 sep 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 sep 2017
Application note Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14 ago 2017
Application note Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12 jul 2017
White paper Revolutionize the automotive cockpit 02 jun 2017
Application note Linux Boot Time Optimizations on DRA7xx Devices 31 mar 2017
Application note Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17 feb 2017
Application note Early Splash Screen on DRA7x Devices 31 ene 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 dic 2016
Application note Gstreamer Migration Guidelines 26 abr 2016
User guide Jacinto6 Android Video Decoder Software Design Specification User's Guide 21 abr 2016
User guide Jacinto6 Android Video Encoder Software Design Specification User's Guide 21 abr 2016
Application note Flashing Binaries to DRA7xx Factory Boards Using DFU 14 abr 2016
Application note Tools and Techniques for Audio Debugging 13 abr 2016
Application note Debugging Tools and Techniques With IPC3.x 30 mar 2016
Technical article Infotainment for the Masses – Volkswagen MIB II Standard powered by TI PDF | HTML 17 feb 2016
EVM User's guide DRA75x and DRA74x EVM CPU Board User's Guide 09 feb 2016
User guide JAMR3 Tuner Application Board User’s Guide 09 feb 2016
Application note Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15 ene 2016
Technical article Difficult to see. Always in motion is the future PDF | HTML 04 ene 2016
Technical article Securing the Scene PDF | HTML 16 dic 2015
Technical article What a journey: from Archimedes to reconfigurable clusters PDF | HTML 23 nov 2015
White paper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14 oct 2014
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 ago 2014

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

J6EVM5777 — Módulo de evaluación DRA7xx

The Jacinto™ DRA7xx evaluation module platform designed to speed up development efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or integrated digital cockpit. To allow scalability and re-use across DRA74x and DRA75x Jacinto (...)

Desde: SVTRONICS INC
Guía del usuario: PDF
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Placa de evaluación

J6PEVM577P — Módulo de evaluación DRA7xP

The DRA77xP/DRA76xP-ACD is an evaluation platform designed to allow scalability and re-use across DRA77xP and DRA76xP JacintoTM Infotainment System-on-Chips (SoCs), it is based on Jacinto DRA77xP SoC that incorporates a heterogeneous, scalable architecture that includes a mix of two ARM Cortex-A15 (...)

Desde: SVTRONICS INC
Guía del usuario: PDF
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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-DRA7X — Kit de desarrollo de software de procesador para procesadores DRA7x Jacinto™: Linux, Android y RTOS

Processor SDK Linux Automotive

Processor SDK Linux Automotive is the foundational software development platform for TI's Jacinto™ DRAx family of Infotainment SoCs. The software framework allows users to develop feature-rich Infotainment solutions such as reconfigurable digital instrument (...)

Guía del usuario: PDF
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Firmware

VCTR-3P-AUTOSAR — Componentes de software de vector AUTOSAR, HSM y de red para la industria automotriz

Vector is the leading manufacturer of software tools and embedded components for the development of electronic systems and networking from CAN to Automotive Ethernet. Vector has been a partner of automotive manufacturers, suppliers and related industries since 1988, providing software components, (...)
Desde: Vector Informatik GmbH
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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

Productos y hardware compatibles

Productos y hardware compatibles

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Sistema operativo (SO)

GHS-3P-INTEGRITY-RTOS — INTEGRITY RTOS de Green Hills

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Desde: Green Hills Software
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Modelo de simulación

DRA75x and DRA74x BSDL Model

SPRM667.ZIP (14 KB) - BSDL Model
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Modelo de simulación

DRA75x and DRA74x IBIS Model

SPRM668.ZIP (18366 KB) - IBIS Model
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Modelo de simulación

DRA75x and DRA74x Thermal Model

SPRM669.ZIP (2 KB) - Thermal Model
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Herramienta de cálculo

CLOCKTREETOOL — Herramienta de árbol de reloj para Sitara, automoción, análisis de visión y procesadores de señal di

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
Guía del usuario: PDF
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Herramienta de diseño

PROCESSORS-3P-SEARCH — MPU basada en Arm, MCU basada en Arm y herramienta de búsqueda de terceros DSP

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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Paquete Pasadores Descargar
FCBGA (ABC) 760 Ver opciones
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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