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DAC de audio

PCM5101A

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DAC estéreo de 2VRMS DirectPath™, 106 dB de audio con interfaz PCM de 32 bits y 384 kHz

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NUEVO TAD5142 PRESENTACIÓN PRELIMINAR DAC de audio estéreo de bajo consumo con control por hardware y rango dinámico de 106 dB With integrated headphone amplifier, HW controlled, QFN package

PCM5101A

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Detalles del producto

Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 106 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 106 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).
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Documentación técnica

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* Data sheet PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface datasheet (Rev. C) PDF | HTML 06 may 2015
EVM User's guide PCM510xEVM-U User Guide (Rev. C) 13 oct 2014
Application note A Low Noise, Low Distortion Design for Antialiasing and Anti-Imaging Filters 27 sep 2000

Diseño y desarrollo

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TSSOP (PW) 20 Ver opciones
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  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
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  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
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