This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.
The nine latches are transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. The Q outputs are in the 3-state condition when the
output-enable (
) input is
high.
Read back is provided through the output-enable (
) input. When is taken low, the data present at
the output of the data latches is allowed to pass back onto the input
data bus. When is taken high,
the output of the data latches is isolated from the D inputs. does not affect the internal
operation of the latches; however, precautions should be taken not to
create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 9-Bit D-Type Trans Read-Back Latch With 3-State Outputs datasheet (Rev. B) | 01 ene 1995 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 dic 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 ago 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 ago 1995 |
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El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Paquete | Pasadores | Descargar |
|---|---|---|
| SOIC (DW) | 24 | Ver opciones |
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