SN74AUC1G74

Name: SN74AUC1G74
Brand: TI
SKU: SN74AUC1G74
Price: 0.1 USD

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Biestable único de tipo D con activación de borde positivo con opciones de eliminación y preajuste

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document-pdfAcrobat SN74AUC1G74 datasheet (Rev. D) (Inglés)

SN74AUC1G74

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Detalles del producto

Number of channels

1

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

275

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

1

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

275

IOL (max) (mA)

9

IOH (max) (mA)

-9

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

DSBGA (YZP)

8

2.8125 mm² 2.25 x 1.25

SSOP (DCT)

8

11.8 mm² 2.95 x 4

UQFN (RSE)

8

2.25 mm² 1.5 x 1.5

VSSOP (DCU)

8

6.2 mm² 2 x 3.1

Available in the Texas Instruments NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 1.5 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments

Available in the Texas Instruments NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 1.5 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

NanoFree Is a trademark of Texas Instruments

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Ver todo 18

	Tipo	Título		Fecha
*	Data sheet	SN74AUC1G74 datasheet (Rev. D)		25 jun 2007
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 dic 2022
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 ene 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 jun 2004
	User guide	Signal Switch Data Book (Rev. A)		14 nov 2003
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices		21 mar 2003
	User guide	AUC Data Book, January 2003 (Rev. A)		01 ene 2003
	Application note	Texas Instruments Little Logic Application Report		01 nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 ago 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 jun 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		27 mar 2002
	More literature	AUC Product Brochure (Rev. A)		18 mar 2002

Diseño y desarrollo

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Placa de evaluación

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