Inicio Lógica y traducción de voltaje Biestables, latches y registros Contadores
Inicio
Lógica y traducción de voltaje
Biestables, latches y registros
Contadores

SN74LV8154-EP

ACTIVO

Contador binario de 16 bits doble con registros de salida de 3 estados de producto mejorado

Haga su pedido ahora
Hoja de datos

SN74LV8154-EP

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Function Counter Bits (#) 16 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Function Counter Bits (#) 16 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 25 ns at 5 V (RCLK to Y)
  • Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 25 ns at 5 V (RCLK to Y)
  • Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV8154 is a dual 16 bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

This 16 bit counter (A or B) feeds a 16 bit storage register and each storage register is further divided into an upper byte and lower byte. The GAL, GAU, GBL, and GBU inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32 bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN.

To ensure the high-impedance state during power up or power down, GAL, GAU, GBL, and GBU should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
open-in-new Buscar otro/a Contadores
Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Funcionalidad similar a la del dispositivo comparado
NUEVO SN74LV393B-EP ACTIVO Contadores binarios dobles de 4 bits mejorados Voltage range (2V to 5.5V), average drive strength (12mA), average propagation delay (9ns)

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 2
Tipo Título Fecha
* Data sheet Dual 16 Bit Binary Counters With 3-State Output Registers datasheet (Rev. A) 10 sep 2007
* VID SN74LV8154-EP VID V6206662 21 jun 2016

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Paquete Pasadores Descargar
TSSOP (PW) 20 Ver opciones
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos