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TLK10081

アクティブ

10Gbps、1 ~ 8 チャネル、マルチレート冗長リンク・アグリゲータ

製品詳細

Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
    Independent Lower Speed Gigabit Serial Lines into a Single
    Higher Speed Gigabit Serial Line with Extensive Media
    Transmission Capabilities.
  • 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Dynamic Port Aggregation Supported
  • Programmable High Speed Redundant Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization on
    Both Low Speed and High Speed Sides
  • MDIO Clause 22 control interface
  • 8B/10B ENDEC Coding Support
  • Raw (Unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800 mW per channel (typ)
  • Rate Matching Support (For compatible data protocols like GE PCS)
  • Full Non-Blocking Receiver Crosspoint Mapping Capability
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable High Speed Lane Alignment Characters
  • Support for Programmable HS/LS 10-Bit Alignment Characters
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package
  • Automatic Digital Multiplexing/De-Multiplexing of 1 to 8
    Independent Lower Speed Gigabit Serial Lines into a Single
    Higher Speed Gigabit Serial Line with Extensive Media
    Transmission Capabilities.
  • 1∼8 × (0.25 to 1.25 Gbps) to 1 x (2 to 10 Gbps) Multiplexing
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Dynamic Port Aggregation Supported
  • Programmable High Speed Redundant Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization on
    Both Low Speed and High Speed Sides
  • MDIO Clause 22 control interface
  • 8B/10B ENDEC Coding Support
  • Raw (Unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800 mW per channel (typ)
  • Rate Matching Support (For compatible data protocols like GE PCS)
  • Full Non-Blocking Receiver Crosspoint Mapping Capability
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable High Speed Lane Alignment Characters
  • Support for Programmable HS/LS 10-Bit Alignment Characters
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package

The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

The TLK10081 is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

The TLK10081 has a low-speed interface which can accommodate one to eight bidirectional serial links running at rates from 250 Mbps to 1.25 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces can operate at rates from 1 Gbps to 10 Gbps. The high speed interface is designed to run at 8 x the low speed serial rate regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so TX may operate in 8:1 mode while RX operates in 1:1 mode. This independence is restricted to using the same low speed line rate. For example, the TX can operate at 8 × 1.25 Gbps while RX operates at 1 × 1.25 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

The TLK10081 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10081 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 10Gbps 1-8 Channel Multi-Rate Serial Link Aggregator データシート 2013年 11月 8日
アプリケーション・ノート Video Aggregation HD-SDI Interface Application Sheet 2014年 10月 1日
アプリケーション・ノート Link Aggregation Interface Application Sheet 2014年 1月 10日
EVM ユーザー ガイド (英語) TLK10022 and TLK10081 EVM User's Guide 2013年 11月 8日
ユーザー・ガイド TLK10022 and TLK10081 Multi-Rate Lane Aggregator EVM GUI User's Guide 2013年 11月 8日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価基板 (EVM) 向けの GUI

SLLC440 TLK10022/81 EVM GUI Software

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア

製品
その他のインターフェイス
TLK10022 10Gbps、デュアルチャネル、マルチレート・ユニバーサル・リンク・アグリゲータ TLK10081 10Gbps、1 ~ 8 チャネル、マルチレート冗長リンク・アグリゲータ
シミュレーション・モデル

TLK10081 Hspice Model

SLLM233.ZIP (9164 KB) - HSpice Model
シミュレーション・モデル

TLK10081 IBIS Model

SLLM234.ZIP (60 KB) - IBIS Model
シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
シミュレーション・ツール

TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

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TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー ガイド: PDF
英語版 (Rev.A): PDF
リファレンス・デザイン

TIDA-00269 — ギガビット・イーサネット・リンク・アグリゲータ・リファレンス・デザイン

The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
試験報告書: PDF
回路図: PDF
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCBGA (CTR) 144 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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