74ACT16841
- Members of the Texas Instruments WidebusTM Family
- Inputs Are TTL-Voltage Compatible
- 3-State Outputs Drive Bus Lines Directly
- Provide Extra Bus Driving/Latches Necessary for Wider Address/Data Paths or Buses With Parity
- Flow-Through Architecture Optimizes PCB Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process - 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Plastic Thin Shrink Small-Outline (DGG) Packages, 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
These 20-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The 'ACT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
A buffered output-enable (1
or 2) input can be
used to place the outputs of the corresponding 10-bit latch in either
a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor
drive the bus lines significantly.
does not
affect the internal operation of the latches. Old data can be
retained or new data can be entered while the outputs are in the
high-impedance state.
The 74ACT16841 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16841 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16841 is characterized for operation from -40°C to 85°C.
관심 가지실만한 유사 제품
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 20-Bit Bus Interface D-Type Latches With 3-State Outputs datasheet (Rev. A) | 1996/04/01 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004/06/22 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997/06/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996/04/01 |
설계 및 개발
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주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치