홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 카운터
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
카운터

CD40102B

활성

CMOS 8단계 프리셋 가능 테이블 2-십진 BCD 동기 다운 카운터

지금 주문
데이터시트

CD40102B

활성
데이터시트 지금 주문

제품 상세 정보

Function Counter Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Presettable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Function Counter Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Positive input clamp diode, Presettable, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOP (NS) 16 79.56 mm² 10.2 x 7.8 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Synchronous or asynchronous preset
  • Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V
  • Cascadable
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Divide-by-"N" counters
    • Programmable timers
    • Interrupt timers
    • Cycle/program counter

CD40102B - 2-Decade BCD Type
CD40103B - 8-Bit Binary Type
  • Synchronous or asynchronous preset
  • Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V
  • Cascadable
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Applications:
    • Divide-by-"N" counters
    • Programmable timers
    • Interrupt timers
    • Cycle/program counter

CD40102B - 2-Decade BCD Type
CD40103B - 8-Bit Binary Type

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period.

When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102B and 25510 for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.

This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse.

The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22.

The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period.

When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102B and 25510 for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.

This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse.

The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22.

The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).
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관심 가지실만한 유사 제품

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비교 대상 장치와 유사한 기능
SN74LV163A 활성 4비트 동기식 이진 카운터 Voltage range (2V to 5.5V), average drive strength (12mA), average propagation delay (9ns)

기술 문서

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모두 보기7
유형 직함 날짜
* Data sheet CD40102B, CD40103B TYPES datasheet (Rev. B) 2003/06/27
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001/12/03

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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패키지 핀 다운로드
PDIP (N) 16 옵션 보기
SOP (NS) 16 옵션 보기
TSSOP (PW) 16 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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  • 팹 위치
  • 조립 위치

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