CD40109B-Q1
- Qualified for Automotive Applications
- Independent of Power Supply Sequence Considerations
- VCC Can Exceed VDD
- Input Signals can Exceed Both VCC and VDD
- Up and Down Level-Shifting Capability
- Three-State Outputs With Separate Enable Controls
- Standardized Symmetrical Output Characteristics
- 100% Tested for Quiescent Current at 20 V
- Maximum Input Current:
- 1 µA at 18 V Over Full Package-Temperature Range
- 100 nA at 18 V and 25°C
- Noise Margin (Full Package-Temperature Range):
- 1 V at VCC = 5 V, VDD = 10 V
- 2 V at VCC = 10 V, VDD = 15 V
- 5-V, 10-V, and 15-V Parametric Ratings
- Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard specifications for Description of ’B’ Series CMOS Devices"
- Latch-Up Performance Meets 50 mA per JESD 78, Class I
- APPLICATIONS
- High-or-Low Level-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussing
- Isolation of Logic Subsystem Using Separate Power Supplies from Supply Sequencing, Supply Loss, and Supply Regulation Considerations
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.
The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
비교 대상 장치와 유사한 기능
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | CD40109B-Q1 CMOS Quad Low-to-High Voltage Level Shifter datasheet (Rev. A) | 2011/08/24 | |
Application note | Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers | PDF | HTML | 2024/05/14 | |
Application brief | Leveraging TXH for High Voltage Level Shifting | PDF | HTML | 2023/07/28 | |
Selection guide | Voltage Translation Buying Guide (Rev. A) | 2021/04/15 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
More literature | Automotive Logic Devices Brochure | 2014/08/27 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
User guide | Signal Switch Data Book (Rev. A) | 2003/11/14 | ||
Application note | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001/12/03 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | 다운로드 |
---|---|---|
SOP (NS) | 16 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치