홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 JK 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
JK 플립플롭

CD4027B-MIL

활성

CMOS 듀얼 J-K 마스터 슬레이브 플립플롭

지금 주문
데이터시트

CD4027B-MIL

활성
데이터시트 지금 주문

제품 상세 정보

Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type TTL Output type Push-Pull Clock frequency (MHz) 12 Supply current (max) (µA) 600 IOL (max) (mA) -1.5 IOH (max) (mA) 1.5 Features Balanced outputs, Clear, Positive edge triggered, Positive input clamp diode, Preset, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type TTL Output type Push-Pull Clock frequency (MHz) 12 Supply current (max) (µA) 600 IOL (max) (mA) -1.5 IOH (max) (mA) 1.5 Features Balanced outputs, Clear, Positive edge triggered, Positive input clamp diode, Preset, Standard speed (tpd > 50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Set-reset capability
  • Static flip-flop operation – retains state indefinitely with clock level either high or low
  • Medium speed operation – 16 MHz (typical) clock toggle rate at 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5 V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC tentative standard No. 138, standard specifications for description of ’B’ series CMOS devices
  • Set-reset capability
  • Static flip-flop operation – retains state indefinitely with clock level either high or low
  • Medium speed operation – 16 MHz (typical) clock toggle rate at 10 V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package-temperature range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • 5 V, 10 V, and 15 V parametric ratings
  • Meets all requirements of JEDEC tentative standard No. 138, standard specifications for description of ’B’ series CMOS devices

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatibile operation with the RCA-CD4013B dual D-type flip-flop.

The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the postitive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.

The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffice), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K flip flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatibile operation with the RCA-CD4013B dual D-type flip-flop.

The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the postitive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.

The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffice), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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기술 문서

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모두 보기8
유형 직함 날짜
* Data sheet CD4027B CMOS Dual J-K Flip Flop datasheet (Rev. D) PDF | HTML 2021/07/14
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001/12/03

설계 및 개발

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패키지 핀 다운로드
CDIP (J) 16 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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