홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 래치
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치

CD74FCT843A

활성

3상 출력을 지원하는 BiCMOS FCT 인터페이스 로직 9비트 비인버팅 트랜스페어런스 래치

지금 주문
데이터시트

CD74FCT843A

활성
데이터시트 지금 주문

제품 상세 정보

Number of channels 9 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 9 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Packaged in Plastic Small-Outline Package
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Packaged in Plastic Small-Outline Package

The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE\) input controls the 3-state outputs. When OE\ is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE\) and clear (CLR\), are ideal for parity-bus interfacing. When PRE\ is low, the outputs are high if OE\ is low. PRE\ overrides CLR\. When CLR\ is low, the outputs are low if OE\ is low. When CLR\ is high, data can be entered into the latch. The device provides noninverted outputs.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0°C to 70°C.

The CD74FCT843A is a 9-bit, bus-interface, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The CD74FCT843A outputs are transparent to the inputs when the latch-enable (LE) input is high. The latches are transparent D-type latches. When LE goes low, the data is latched. The output-enable (OE\) input controls the 3-state outputs. When OE\ is high, the outputs are in the high-impedance state. The latch operation is independent of the state of the output enable. This device, having preset (PRE\) and clear (CLR\), are ideal for parity-bus interfacing. When PRE\ is low, the outputs are high if OE\ is low. PRE\ overrides CLR\. When CLR\ is low, the outputs are low if OE\ is low. When CLR\ is high, data can be entered into the latch. The device provides noninverted outputs.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The CD74FCT843A is characterized for operation from 0°C to 70°C.
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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74AHCT16373 활성 3상 출력을 지원하는 16비트 트랜스페어런스 D형 래치 Larger voltage range (2V to 5.5V)
비교 대상 장치와 유사한 기능
SN74ACT373 활성 3상 출력을 지원하는 8진 D형 트랜스페어런스 래치 Voltage range (4.5V to 5.5V), average drive strength (24mA), average propagation delay (8ns)

기술 문서

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모두 보기8
유형 직함 날짜
* Data sheet BiCMOS 9-Bit Bus-Interface D-Type Latch With 3-State Outputs datasheet 2000/07/02
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
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SOIC (DW) 24 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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