CY54FCT573T
- Function and Pinout Compatible With FCT and F Logic
- Reduced VOH(Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- 3-State Outputs
- CY54FCT573T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT573T
- 64-mA Output Sink Current
- 32-mA Output Source Current
The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | 8-Bit Latches With 3-State Outputs datasheet | 2001/10/01 | |
* | SMD | CY54FCT573T SMD 5962-92238 | 2016/06/21 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004/06/22 | ||
User guide | CYFCT Parameter Measurement Information | 2001/04/02 | ||
Selection guide | Advanced Bus Interface Logic Selection Guide | 2001/01/09 |
설계 및 개발
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주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치