홈 로직 및 전압 변환 로직 게이트 NAND 게이트
홈
로직 및 전압 변환
로직 게이트
NAND 게이트

SN54LVC00A

활성

군사용 4채널, 2입력, 2V~3.6V NAND 게이트

지금 주문
데이터시트

SN54LVC00A

활성
데이터시트 지금 주문

제품 상세 정보

Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Military Operating temperature range (°C) -55 to 125
Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • SN74LVC00A operates from 1.65V to 3.6V
  • SN54LVC00A operates from 2V to 3.6V
  • SNx4LVC00A specified from –40°C to +85°C and –40°C to +125°C
  • SN54LVC00A specified from –55°C to +125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.3ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • SN74LVC00A operates from 1.65V to 3.6V
  • SN54LVC00A operates from 2V to 3.6V
  • SNx4LVC00A specified from –40°C to +85°C and –40°C to +125°C
  • SN54LVC00A specified from –55°C to +125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.3ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250 mA per JESD 17
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7V to 3.6V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.

The SNx4LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.

The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7V to 3.6V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.

The SNx4LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.
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기술 문서

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모두 보기28
유형 직함 날짜
* Data sheet SNx4LVC00A Quadruple 2-Input Positive-NAND Gates datasheet (Rev. S) PDF | HTML 2024/03/01
* SMD SN54LVC00A SMD 5962-97533 2016/06/21
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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패키지 핀 다운로드
CDIP (J) 14 옵션 보기
CFP (W) 14 옵션 보기
LCCC (FK) 20 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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