홈 로직 및 전압 변환 전압 변환기 및 레벨 시프터 고정 방향 전압 변환기
홈
로직 및 전압 변환
전압 변환기 및 레벨 시프터
고정 방향 전압 변환기
신규

SN54SC4T125-SEP

활성

방사능 내성, 4비트 고정 방향 레벨 변환기

지금 주문
데이터시트

SN54SC4T125-SEP

활성
데이터시트 지금 주문

제품 상세 정보

Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Applications GPIO Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 5.5 Data rate (max) (Mbps) 100 IOH (max) (mA) -16 IOL (max) (mA) -16 Supply current (max) (µA) 5.5 Features Balanced outputs, Over-voltage tolerant inputs, Voltage translation Input type TTL-Compatible CMOS Output type 3-State Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
filter 기타 고정 방향 전압 변환기 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기5
유형 직함 날짜
* Data sheet SN54SC4T125-SEP Radiation Tolerant, Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet PDF | HTML 2023/11/15
* Radiation & reliability report SN54SC4T125-SEP Single Event Effects Report PDF | HTML 2023/12/05
* Radiation & reliability report SN54SC4T125-SEP Total Ionizing Dose (TID) Report PDF | HTML 2023/12/01
* Radiation & reliability report SN54SC4T125-SEP Production Flow and Reliability Report PDF | HTML 2023/11/09
Application note Understanding Transient Drive Strength vs. DC Drive Strength in CMOS Output Buffers PDF | HTML 2024/05/14

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없습니다
패키지 핀 다운로드
TSSOP (PW) 14 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상