SN64BCT244
- State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
- 3-State Outputs Drive Bus Lines or Buffer-Memory Address Registers
- P-N-P Inputs Reduce DC Loading
- High-Impedance State During Power Up and Power Down
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (N)
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the SN64BCT240 and SN64BCT241, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE and inputs.
The SN64BCT244 is organized as two 4-bit buffers/line drivers with separate output-enable () inputs. When is low, the device passes data from the A inputs to the Y outputs. When is high, the outputs are in the high-impedance state.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.
The SN64BCT244 is characterized for operation from -40°C to 85°C.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | Octal Buffer/Driver With 3-State Outputs datasheet (Rev. A) | 1994/01/01 | |
Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
Application note | Live Insertion | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | 다운로드 |
---|---|---|
SOIC (DW) | 20 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치