SN64BCT25245
- State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
- Designed to Facilitate Incident-Wave Switching for Line Impedances of 25
or Greater - Distributed VCC and GND Pins Minimize Noise Generated by the Simultaneous Switching of Outputs
- Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
- High-Impedance State During Power Up and Power Down
- ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
The SN64BCT25245 is a 25-
octal bus transceiver designed for asynchronous communication between
data buses. It improves both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented transceivers.
The device allows data transmission from the A bus to the B bus or
from the B bus to the A bus depending upon the logic level at the
direction-control (DIR) input. The output-enable (
) input can disable the device so
that both buses are effectively isolated.
This transceiver is capable of sinking 188-mA IOL,
which facilitates switching 25- transmission lines on the incident wave. The
distributed VCC and GND pins minimize switching noise for
more reliable system operation.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.
The SN64BCT25245 is characterized for operation from -40°C to 85°C and 0°C to 70°C.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | 25 Ohm Octal Bus Transceiver datasheet (Rev. A) | 1993/12/01 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021/07/26 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
| Application note | Live Insertion | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| SOIC (DW) | 24 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치