SN74F657
- Combines ´F245 and ´F280B Functions in One Package
- High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
- High Output Drive and Light Bus Loading
- 3-State B Outputs Sink 64 mA and Source 15 mA
- Input Diodes for Termination Effects
- Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.
The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.
When the output enable (
)
input is high, both the A and B ports are placed in a high-impedance
state (disabled). The ODD/EVEN\ input allows the user to select
between odd or even parity systems. When transmitting from A port to
B port (T/R\ high), PARITY is an output from the generator/checker.
When receiving from B port to A port (T/R\ low), PARITY is an input.
When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.
When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:
- 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
- 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.
The SN74F657 is characterized for operation from 0°C to 70°C.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Octal Transceiver With Parity Generator/Checker And 3-State Outputs datasheet (Rev. A) | 1993/10/01 | |
| Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997/08/01 | ||
| Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| SOIC (DW) | 24 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치