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SN74FB1653

활성

버퍼 클록 라인을 지원하는 17비트 TTL/BTL 범용 저장소 트랜시버

지금 주문
데이터시트

SN74FB1653

활성
데이터시트 지금 주문

제품 상세 정보

Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
Technology family FB Applications GTL Rating Catalog Operating temperature range (°C) 0 to 70
HLQFP (PCA) 100 256 mm² 16 x 16
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal
  • Compatible With IEEE Std 1194.1-1991 (BTL)
  • LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
  • Open-Collector B\-Port Outputs Sink 100 mA
  • B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
  • High-Impedance State During Power Up and Power Down
  • Selectable Clock Delay
  • TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
  • BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.

The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.

The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.

The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).

BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

BG VCC and BG GND are the supply inputs for the bias generator.

VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.

Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.
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기술 문서

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모두 보기13
유형 직함 날짜
* Data sheet SN74FB1653 datasheet (Rev. H) 2004/03/10
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Voltage Translation Buying Guide (Rev. A) 2021/04/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) 1997/03/01
Application note Next-Generation BTL/Futurebus Transceivers Allow Single-Sided SMT Manufacturing (Rev. C) 1997/03/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

SN74FB1653 IBIS Model (Rev. C)

SCBM012C.ZIP (26 KB) - IBIS Model
다운로드
패키지 핀 다운로드
HLQFP (PCA) 100 옵션 보기
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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