SN74LS297
- Digital Design Avoids Analog Compensation Errors
- Easily Cascadable for Higher Order Loops
- Useful Frequency from DC to:
- 50 MHz Typical (K Clock)
- 35 MHz Typical (I/D Clock)
The SN54LS297 and SN74LS297 devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first order phase-locked loops as described in Figure 1.
Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and D are all programmed high, the K counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A through D inputs can maximize the overall performance of the digital phase-locked loop.
The 'LS297 can perform the classic first-order phase-locked loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the divide-by-N modulos will determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D Clock /2N(Hz).
기술 문서
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | Digital Phase-Locked-Loop Filters datasheet | 1988/03/01 | |
Selection guide | Logic Guide (Rev. AB) | 2017/06/12 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015/12/02 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007/01/16 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002/08/29 | ||
Application note | Designing With Logic (Rev. C) | 1997/06/01 | ||
Application note | Designing with the SN54/74LS123 (Rev. A) | 1997/03/01 | ||
Application note | Digital PLL Design Using the SN54/74LS297 (Rev. B) | 1997/03/01 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996/10/01 | ||
Application note | Live Insertion | 1996/10/01 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
패키지 | 핀 | 다운로드 |
---|---|---|
PDIP (N) | 16 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치