제품 상세 정보

Function General-purpose timer Iq (typ) (mA) 0.17 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 15 Supply voltage (min) (V) 1
Function General-purpose timer Iq (typ) (mA) 0.17 Rating Catalog Operating temperature range (°C) 0 to 70 Supply voltage (max) (V) 15 Supply voltage (min) (V) 1
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Very Low Power Consumption
    1 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail
    to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 1 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2
  • Very Low Power Consumption
    1 mW Typ at VDD = 5 V
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail
    to Rail
  • High Output-Current Capability
    Sink 100 mA Typ
    Source 10 mA Typ
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 1 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015.2

The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM

process. The

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

The TLC551C is characterized for operation from 0°C to 7

The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM

process. The

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC551 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

The TLC551C is characterized for operation from 0°C to 7

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
TLC555 활성 2.1MHz, 250µA, 저전력 타이머 Higher max frequency operation and slightly higher power

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기1
유형 직함 날짜
* Data sheet LinCMOS Timers datasheet (Rev. B) 1997/09/25

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

TLC551 TINA-TI Astable Reference Design

SLAM126.TSC (96 KB) - TINA-TI Reference Design
시뮬레이션 모델

TLC551 TINA-TI Mono Reference Design

SLAM125.TSC (155 KB) - TINA-TI Reference Design
시뮬레이션 모델

TLC551 TINA-TI Spice Model

SLAM128.ZIP (9 KB) - TINA-TI Spice Model
시뮬레이션 모델

TLC551 and TLC552 PSpice Model (Rev. A)

SLAM127A.ZIP (29 KB) - PSpice Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
패키지 다운로드
PDIP (P) 8 옵션 보기
SOIC (D) 8 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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