제품 상세 정보

Resolution (Bits) 10 Sample rate (max) (ksps) 2000 Number of input channels 4 Interface type Parallel Architecture Pipeline Input type Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 3 Input voltage range (min) (V) 0.8 Features Oscillator Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 13.5 Analog supply (min) (V) 2.7 Analog supply voltage (max) (V) 5.5 SNR (dB) 58.1 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
Resolution (Bits) 10 Sample rate (max) (ksps) 2000 Number of input channels 4 Interface type Parallel Architecture Pipeline Input type Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 3 Input voltage range (min) (V) 0.8 Features Oscillator Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 13.5 Analog supply (min) (V) 2.7 Analog supply voltage (max) (V) 5.5 SNR (dB) 58.1 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
SOIC (DW) 28 184.37 mm² 17.9 x 10.3 TSSOP (PW) 28 62.08 mm² 9.7 x 6.4
  • 2 MSPS Max Throughput at 10 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX
  • 3 MSPS Max Throughput at 8 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX
  • 7 MSPS Max Throughput at 4 Bit (Single Channel), ±0.4 LSB DNL, ±0.4 LSB INL MAX
  • No Missing Code for External Clock Up to 15 MHz at 5.5 V, 12 MHz at 2.7 V
  • ENOB 9.4 Bit, SINAD 57.8 dB, SFDR
    -70.8 dB, THD -68.8 dB, at fi = 800 kHz,
    10 Bit
  • Wide Input Bandwidth for Undersampling (75 MHz at 1 dB, >120 MHz at -3 dB) at
    Rs = 1 k
  • Software Programmable Power Down, (1 uA), Auto Powerdown (120 uA)
  • Single Wide Range Supply 2.7 VDC to 5.5 VDC
  • Low Supply Current 11 mA at 5.5 V, 10 MHz; 7 mA at 2.7 V, 8 MHz Operating
  • Simultaneous Sample and Hold:
  • Dual Sample and Hold Matched Channels
  • Multi Chip Simultaneous Sample and Hold Capable
  • Programmable Conversion Modes: Interrupt-Driven for Shorter Latency Continuous Modes Optimized for MIPS Sensitive DSP Solutions
  • Built-In Internal/System Mid-Scale Error Calibration
  • Built-In Mux With 2 Differential or 4 Single-Ended Input Channels
  • Low Input Capacitance (10 pF Max Fixed, 1 pF Max Switching)
  • DSP/u P-Compatible Parallel Interface
  • 2 MSPS Max Throughput at 10 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX
  • 3 MSPS Max Throughput at 8 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX
  • 7 MSPS Max Throughput at 4 Bit (Single Channel), ±0.4 LSB DNL, ±0.4 LSB INL MAX
  • No Missing Code for External Clock Up to 15 MHz at 5.5 V, 12 MHz at 2.7 V
  • ENOB 9.4 Bit, SINAD 57.8 dB, SFDR
    -70.8 dB, THD -68.8 dB, at fi = 800 kHz,
    10 Bit
  • Wide Input Bandwidth for Undersampling (75 MHz at 1 dB, >120 MHz at -3 dB) at
    Rs = 1 k
  • Software Programmable Power Down, (1 uA), Auto Powerdown (120 uA)
  • Single Wide Range Supply 2.7 VDC to 5.5 VDC
  • Low Supply Current 11 mA at 5.5 V, 10 MHz; 7 mA at 2.7 V, 8 MHz Operating
  • Simultaneous Sample and Hold:
  • Dual Sample and Hold Matched Channels
  • Multi Chip Simultaneous Sample and Hold Capable
  • Programmable Conversion Modes: Interrupt-Driven for Shorter Latency Continuous Modes Optimized for MIPS Sensitive DSP Solutions
  • Built-In Internal/System Mid-Scale Error Calibration
  • Built-In Mux With 2 Differential or 4 Single-Ended Input Channels
  • Low Input Capacitance (10 pF Max Fixed, 1 pF Max Switching)
  • DSP/u P-Compatible Parallel Interface

The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (uP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages (2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving feature is further enhanced with a software power-down feature (1 uA maximum) and auto power-down (1 uA maximum) feature.

Many programmable features make this device a flexible general-purpose data converter. The device can be configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an external clock source (CLKIN). Four different modes of conversion are available for different applications. The interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication applications. Conversion is started by the RD\ signal, which can also be used for reading data, to maximize the throughput. Conversion can be started either by the RD\ or CSTART\ signal when the device is operating in the interrupt-driven modes. The dedicated conversion start pin, CSTART\, provides a mechanism to simultaneously sample and convert multiple channels when multiple converters are used in an application.

The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal processing (DSP) companion for mobile communication applications. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range.

The features that make this device truly a DSP friendly converter include: 1) programmable continuous conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation from 0°C to 70°C. The TLV1562I is characterized for operation over the full industrial temperature range of -40°C to 85°C.

The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (uP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages (2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving feature is further enhanced with a software power-down feature (1 uA maximum) and auto power-down (1 uA maximum) feature.

Many programmable features make this device a flexible general-purpose data converter. The device can be configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an external clock source (CLKIN). Four different modes of conversion are available for different applications. The interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication applications. Conversion is started by the RD\ signal, which can also be used for reading data, to maximize the throughput. Conversion can be started either by the RD\ or CSTART\ signal when the device is operating in the interrupt-driven modes. The dedicated conversion start pin, CSTART\, provides a mechanism to simultaneously sample and convert multiple channels when multiple converters are used in an application.

The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal processing (DSP) companion for mobile communication applications. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range.

The features that make this device truly a DSP friendly converter include: 1) programmable continuous conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation from 0°C to 70°C. The TLV1562I is characterized for operation over the full industrial temperature range of -40°C to 85°C.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
ADS7863A 활성 듀얼, 2MSPS, 12비트, 2+2 또는 3+3채널, 동시 샘플링 SAR ADC Higher resolution, different architecture, different interface

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
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모두 보기3
유형 직함 날짜
* Data sheet Low Power, Dual Sample-and-Hold Parallel Analog-to-Digital Converters datasheet 1998/09/25
EVM User's guide TLV1562 Evaluation Module (Rev. A) 2000/09/08
Application note Interfacing the TLV1562 Parallel ADC to the TMS320C54x DSP 1999/07/09

설계 및 개발

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계산 툴

ANALOG-ENGINEER-CALC — 아날로그 엔지니어의 계산기

The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 다운로드
SOIC (DW) 28 옵션 보기
TSSOP (PW) 28 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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