XIO2001
- Full ×1 PCI Express™ Throughput
- Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
- Fully Compliant With PCI Express Base Specification, Revision 2.0
- Fully Compliant With PCI Local Bus Specification, Revision 2.3
- PCI Express Advanced Error Reporting Capability Including ECRC Support
- Support for D1, D2, D3hot, and D3cold
- Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
- Wake Event and Beacon Support
- Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
- Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
- Optional Spread Spectrum Reference Clock is Supported
- Robust Pipeline Architecture to Minimize Transaction Latency
- Full PCI Local Bus 66-MHz/32-Bit Throughput
- Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
- Internal PCI Arbiter Supporting Up to 6 External PCI Masters
- Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
- External PCI Bus Arbiter Option
- PCI Bus LOCK Support
- JTAG/BS for Production Test
- PCI-Express CLKREQ Support
- Clock Run and Power Override Support
- Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
- PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
- Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
- Five 3.3-V, Multifunction, General-Purpose I/O Terminals
- Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
- Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package
The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.
The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.
The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.
기술 문서
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | XIO2001 PCIe to PCI Bus Translation Bridge datasheet (Rev. J) | 2020/12/06 | |
| * | Errata | XIO2001 Errata (Rev. B) | 2012/12/17 | |
| Application note | XIO2001 Implementation Guide. (Rev. D) | 2014/06/19 | ||
| EVM User's guide | XIO2001 EVM User Guide (Rev. B) | 2014/06/12 | ||
| Application note | XIO2000A to XIO2001 Change Document | 2009/05/28 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
XIO2001EVM — XIO2001 평가 모듈
The XIO2001EVM evaluation module (EVM) implements a peripheral component interconnect (PCI) express to PCI bridge circuit using the Texas Instruments XIO2001 PCI Express® (PCIe) to PCI bus translation bridge. Designed as a half-width x1 PCIe add-in card, the (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | 다운로드 |
|---|---|---|
| HTQFP (PNP) | 128 | 옵션 보기 |
| NFBGA (ZAJ) | 144 | 옵션 보기 |
| NFBGA (ZWS) | 169 | 옵션 보기 |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.