產品詳細資料

Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 80 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 Supply current (max) (µA) 80 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35
  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

     

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

     

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The 'ACT16541 are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1 and 1 or 2 and 2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state.

The 74ACT16541 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16541 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16541 is characterized for operation from -40°C to 85°C.

 

 

The 'ACT16541 are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1 and 1 or 2 and 2) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state.

The 74ACT16541 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16541 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16541 is characterized for operation from -40°C to 85°C.

 

 

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類型 標題 日期
* Data sheet 16-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. A) 1996年 4月 1日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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模擬型號

74ACT16541 Behavioral SPICE Model

SCAM081.ZIP (7 KB) - PSpice Model
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SSOP (DL) 48 檢視選項

訂購與品質

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  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

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