產品詳細資料

Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 300 Architecture Pipeline SNR (dB) 71.2 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 80 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 300 Architecture Pipeline SNR (dB) 71.2 ENOB (bit) 11.5 SFDR (dB) 90 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (RTV) 32 25 mm² 5 x 5
  • 1 GHz Full Power Bandwidth
  • Internal Reference and Sample-and-Hold Circuit
  • Low Power Consumption
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Single +3.0V Supply Operation
  • Power-Down Mode
  • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution 12 Bits
  • Conversion Rate 80 MSPS
  • SNR (fIN = 170 MHz) 68 dBFS (typ)
  • SFDR (fIN = 170 MHz) 86 dBFS (typ)
  • Full Power Bandwidth 1 GHz (typ)
  • Power Consumption 300 mW (typ)

All trademarks are the property of their respective owners.

  • 1 GHz Full Power Bandwidth
  • Internal Reference and Sample-and-Hold Circuit
  • Low Power Consumption
  • Data Ready Output Clock
  • Clock Duty Cycle Stabilizer
  • Single +3.0V Supply Operation
  • Power-Down Mode
  • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

  • Resolution 12 Bits
  • Conversion Rate 80 MSPS
  • SNR (fIN = 170 MHz) 68 dBFS (typ)
  • SFDR (fIN = 170 MHz) 86 dBFS (typ)
  • Full Power Bandwidth 1 GHz (typ)
  • Power Consumption 300 mW (typ)

All trademarks are the property of their respective owners.

The ADC12C080 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C080 may be operated from a single +3.0V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12C080 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

The ADC12C080 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 80 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C080 may be operated from a single +3.0V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12C080 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC12C080 is available in a 32-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 2
類型 標題 日期
* Data sheet ADC12C080 12-Bit, 65/80 MSPS A/D Converter datasheet (Rev. C) 2013年 4月 19日
User guide ADC14C105EB and ADC12C105EB Evaluation Board User Guide (Rev. A) 2013年 10月 11日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
封裝 引腳 下載
WQFN (RTV) 32 檢視選項

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片