ADC12DJ5200SE
- ADC core:
- 12-bit resolution
- Up to 10.4 GSPS in single-channel mode
- Up to 5.2 GSPS in dual-channel mode
- Single Ended 50 Ω Inputs:
- Analog input range (–3 dB): 2 to 6.3 GHz
- Full-scale input power (4.5 GHz): - 1.25 dBm
- Flexible V CM: AC coupled with no DC path to GND or supply
- Performance specifications:
- Noise floor (2.3 GHz, –20 dBFS, INPUT FS = 1.5 dBm):
- Dual-channel mode: –149 dBFS/Hz
- Single-channel mode: –151.5 dBFS/Hz
- ENOB (dual channel, F IN = 2.3 GHz): 8.5 Bits
- Noise floor (2.3 GHz, –20 dBFS, INPUT FS = 1.5 dBm):
- Noiseless aperture delay (t AD) adjustment:
- Precise sampling control: 19-fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16 Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power: +26.25 dBm (+ 27.5 dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4 W
- Power supplies: 1.1 V, 1.9 V
The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3 dB input frequency range of 2 to 6.3 GHz enables direct RF sampling of S-band and C-band for frequency agile systems.
The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC12DJ5200SE 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) with Integrated Baluns datasheet (Rev. A) | PDF | HTML | 2023年 5月 8日 |
| User guide | ADCxxDJxx00RF Evaluation Module User's Guide (Rev. B) | PDF | HTML | 2023年 3月 2日 |
設計與開發
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ADC12DJ5200SEEVM — 適用於單端輸入射頻取樣12 位元 ADC 的 ADC12DJ5200SE 評估模組
ADC12DJ5200SE 評估模組 (EVM) 是用於評估 ADC12DJ5200SE 類比轉數位轉換器 (ADC) 的平台。ADC12DJ5200SE 是雙通道 12 位元 ADC，可在雙通道模式下以高達每秒 5.2 千兆次取樣 (GSPS)，或在單通道模式下以 10.4 GSPS 的取樣速率運作。ADC12DJ5200SEEVM 輸出資料透過標準 JESD204C 高速序列介面傳輸。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 引腳 | 下載 |
|---|---|---|
| FCCSP (AAV) | 144 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
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