ADC32RF55
- 14-Bit, dual channel 2.6 to 3-GSPS ADC
- Noise spectral density:
- NSD = -155.6 dBFS/Hz (no AVG)
- NSD = -158.1 dBFS/Hz (2x AVG)
- NSD = -160.4 dBFS/Hz (4x AVG)
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 50 fs
- Low close-in residual phase noise:
- -127 dBc/Hz at 10 kHz offset
- Spectral performance (f IN = 1 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 62.3 dBFS
- SFDR HD2,3: 63 dBc
- SFDR worst spur: 85 dBFS
- Spectral performance (f IN = 1.8 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 63 dBFS
- SFDR HD2,3: 68 dBc
- SFDR worst spur: 86 dBFS
- Input fullscale: 1.1 to 1.35 Vpp (2 to 3.5 dBm)
- Code error rate (CER): 10 -15
- Full power input bandwidth (-3 dB): 2.75 GHz
- JESD204B serial data interface
- Maximum lane rate: 13 Gbps
- Supports subclass 1 deterministic latency
- Digital down-converters
- Up to four DDC per ADC channel
- Complex output: 4x to 128x decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1 us
- Power consumption: 2.6 W/channel (2x AVG)
- Power supplies: 1.8 V, 1.2 V
The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz.
Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps.
The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter datasheet (Rev. B) | PDF | HTML | 2023年 8月 21日 |
| Application brief | Noise Spectral Density: A Better Way (Rev. A) | PDF | HTML | 2024年 1月 7日 | |
| Application note | Improve SFDR Using Calibration in High-Speed ADCs | PDF | HTML | 2023年 6月 19日 | |
| Application note | Getting the Most of Your Data Converter Clocking System Using LMX1204 | PDF | HTML | 2022年 6月 23日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC32RF55EVM — 適用於具有低 NSD 的雙通道 14 位元 3-GSPS 射頻取樣 ADC 的 ADC32RF55 評估模組
ADC32RF55 評估模組 (EVM) 是一個展示 ADC32RF55 高速、JESD204B 介面類比轉數位轉換器 (ADC) 性能的平台。板載電壓穩壓、時鐘解決方案 (LMK04832)、變壓器耦合類比輸入及 USB 介面，可輕鬆評估 ADC32RF55。
透過現場可編程邏輯閘陣列 (FPGA) 夾層介面卡 (FMC) 連接器與 TSW14J58EVM (單獨出售) 接合，可以可使用高速數據轉換器專業軟體 (DATACONVERTERPRO-SW) 輕鬆評估及檢視 JESD204B 介面的數據擷取 (最高 1.5 GB)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 引腳 | 下載 |
|---|---|---|
| VQFNP (RTD) | 64 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。