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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC34J42

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四通道、14 位元、50-MSPS 類比轉數位轉換器 (ADC)

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ADC34J42

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 50 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 491 Architecture Pipeline SNR (dB) 72.8 ENOB (bit) 11.9 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 50 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 450 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 491 Architecture Pipeline SNR (dB) 72.8 ENOB (bit) 11.9 SFDR (dB) 93 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Quad Channel
  • 14-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Supports Subclass 0, 1, 2
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Quad Channel
  • 14-Bit Resolution
  • Single 1.8-V Supply
  • Flexible Input Clock Buffer with Divide-by-1, -2, -4
  • SNR = 72 dBFS, SFDR = 86 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 203 mW/Ch at 160 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither
  • JESD204B Serial Interface:
    • Supports Subclass 0, 1, 2
    • Supports One Lane per ADC up to 160 MSPS
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible with 12-Bit Version
  • Package: VQFN-48 (7 mm × 7 mm)

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.

The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
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類型 標題 日期
* Data sheet ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) PDF | HTML 2014年 11月 10日
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 2018年 8月 24日

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ADC34J42EVM — ADC34J42 四通道、14 位元、50-MSPS 類比轉數位轉換器評估模組

ADC34J42 EVM 展示了低功耗四路 50Msps 14 位元 ADC 的性能。其中包括 ADC34J42 裝置、LMK04828 提供的 JESD204B 計時及 TI 電壓穩壓器，以提供必要的電壓。ADC 的輸入預設連接至變壓器輸入，可連接至 50 ohm 單端訊號來源。時鐘參考輸入可透過變壓器輸入提供，並可連接至 50 ohm 單端時鐘來源。板載 LMK04828 可用於產生必要的 JESD204B 時鐘。透過板載 USB 連接和 GUI 提供暫存器存取權。

使用指南: PDF
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TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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ADC34J45 IBIS Model

SBAM204.ZIP (79 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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